Circuit and method to increase read margin in non-volatile memories using a differential sensing circuit
First Claim
1. A differential sensing circuit, comprising:
- a first current-to-voltage converter;
a first current subtraction circuit having an erase reference cell,wherein a first input terminal of the first current-to-voltage converter is coupled to the first current subtraction circuit;
a second current-to-voltage converter; and
a second current subtraction circuit having a program reference cell,wherein a first input terminal of the second current-to-voltage converter is coupled to the second current subtraction circuit,wherein both the first and second current subtraction circuits are coupled to a memory access bias signal, andwherein outputs of the first and second current-to-voltage converts are compared to generate an enhanced read margin output.
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Abstract
A differential sensing circuit and method for enhancing read margin of a memory device are disclosed. The differential sensing circuit includes a first current-to-voltage converter. The circuit includes a first current subtraction circuit having an erase reference cell. A first input terminal of the first current-to-voltage converter is coupled to the first current subtraction circuit. The circuit includes a second current-to-voltage converter. The circuit also includes a second current subtraction circuit having a program reference cell. A first input terminal of the second current-to-voltage converter is coupled to the second current subtraction circuit. Both the first and second current subtraction circuits are coupled to a memory access bias signal. Outputs of the first and second current-to-voltage converters are compared to generate an enhanced read margin output.
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Citations
18 Claims
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1. A differential sensing circuit, comprising:
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a first current-to-voltage converter; a first current subtraction circuit having an erase reference cell, wherein a first input terminal of the first current-to-voltage converter is coupled to the first current subtraction circuit; a second current-to-voltage converter; and a second current subtraction circuit having a program reference cell, wherein a first input terminal of the second current-to-voltage converter is coupled to the second current subtraction circuit, wherein both the first and second current subtraction circuits are coupled to a memory access bias signal, and wherein outputs of the first and second current-to-voltage converts are compared to generate an enhanced read margin output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device with an enhanced read margin, comprising:
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a first current subtraction stack having an erase reference cell coupled to a first current-to-voltage converter; a second current subtraction stack having a program reference cell coupled to a second current-to-voltage converter; and a matrix cell stack coupled to both the first and second current subtraction stacks and coupled to provide a memory access bias signal, wherein output terminals of both the first and second current-to-voltage converters are coupled to a comparator circuit for generating an enhanced read margin output. - View Dependent Claims (10, 11)
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12. A method for improving read margin of a memory device, comprising:
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generating a memory access bias signal; generating an erase current in response to the memory access bias signal; mirroring the erase current through an erase reference cell stack; mirroring the erase current through a program reference cell stack; generating a program current in response to the memory access bias signal; mirroring a program current through a program reference cell stack; and mirroring the program current through the erase reference cell stack. - View Dependent Claims (13, 14, 15, 16)
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17. A method for enhancing read margin of a memory device, comprising:
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subtracting a first current component from a second current component to generate a first differential current, wherein the first differential current is generated in accordance with an erase reference operation of the memory device; subtracting a third current component from a fourth current component to generate a second differential current, wherein the second differential current is generated in accordance with a program reference operation of the memory device; generating a first voltage component substantially proportional to the first differential current corresponding to a memory access bias signal; generating a second voltage component substantially proportional to the second differential current corresponding to the memory access bias signal; and comparing the first and second voltage components to generate an enhanced read margin output. - View Dependent Claims (18)
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Specification