Symmetrically operating single-ended input buffer devices and methods

• US 7,859,916 B2
• Filed: 12/18/2007
• Issued: 12/28/2010
• Est. Priority Date: 12/18/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Amirabadi, Yadollah Eslami
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/002,829
• Publication Number:
  US 20090154255A1
• Time in Patent Office: 1,106 Days
• Field of Search: 365/189.05, 365/63
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03F 2203/45091 Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor that charges and discharges the drain of the second transistor responsive to the input signal transitioning to mimic the second input node transitioning in the direction opposite to the transition of the input signal, while the reference signal at the second input node is maintained at a constant voltage level.

Claims

1. An input buffer comprising:

a first amplifier circuit having an output node, the first amplifier circuit coupled to receive a first input signal and a second input signal, the first amplifier circuit operable to generate an output signal in response to the first input signal transitioning, the first amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transition of the first input signal in a manner such that the rate at which the first amplifier circuit generates the output signal increases; and

a second amplifier circuit being coupled in parallel to the first amplifier circuit and coupled to the output node, the second amplifier circuit being configured complementary respective to the first amplifier circuit and further coupled to receive the first input signal and the second input signal, the second amplifier circuit operable to generate the output signal in response to the first input signal transitioning, the second amplifier circuit being capacitively coupled to receive a portion of the first input signal relative to the transitioning of the first input signal in a manner such that the rate at which the second amplifier circuit generates the output signal increases.

2. The input buffer of claim 1 wherein the first amplifier circuit comprises a first input transistor coupled to receive the first input signal and a second input transistor coupled to receive the second input signal, and wherein second amplifier circuit comprises a third input transistor coupled to receive the first input signal and a fourth input transistor coupled to receive the second input signal.

3. The input buffer of claim 2 wherein the ON-resistance of the second input transistor is adjusted relative to the first input signal received by the first input transistor, and wherein the ON-resistance of the second input transistor is adjusted relative to the first input signal received by the third input transistor transitioning.

4. The input buffer of claim 1 wherein the amplifier circuits are coupled between a supply voltage and ground.

5. The input buffer of claim 4 wherein the first amplifier circuit drives the output node towards the supply voltage as the input signal transitions and the second amplifier circuit drives the output node towards ground as the input signal transitions.

6. The input buffer of claim 5 wherein the output signal at the output node is propagated through an output conditioning circuit comprising a plurality of inverters coupled in series.

7. A digital device comprising:

a memory array from which data are read and to which data are written;

a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling write data signals from the externally accessible data bus terminals to the memory array and read data signals from the memory array to the externally accessible data bus terminals; and

a plurality of buffers coupled to one of the externally accessible terminals through which at least one of a command signals, address signals, or write data signals are coupled, at least one of the buffers comprising;

a first amplifier circuit and a second amplifier circuit coupled in parallel to the first amplifier circuit, the second amplifier circuit have a topology that is complementary to the topology of the first amplifier circuit, each of the amplifier circuits comprising;

an output node;

a first transistor having a first terminal adapted to receive a first input signal; and

a second transistor having a second terminal, capacitively coupled to the first terminal of the first transistor to provide a portion of the first input signal to the second transistor in a manner such that the drive strength of the amplifier circuit is adjusted as an output signal is generated at the output node.

8. The digital device of claim 7 wherein the drive strength of the amplifier that is adjusted mimics a second input signal received at a third terminal of the second transistor that transitions in the opposite direction relative to the first input signal transitioning at the first terminal.

9. The digital device of claim 8 wherein the second input signal maintains a constant voltage level.

10. The digital device of claim 8 wherein the first terminal comprises a gate terminal of the first transistor, the second terminal comprises a drain terminal of the second transistor and the third terminal comprises a gate terminal of the second transistor.

11. The digital device of claim 7 wherein the amplifier circuit outputs a logic state “

1”

at the output node when the magnitude of the first input signal is less than the magnitude of the second input signal, and the amplifier circuit outputs a logic state “

0”

at the output node when the magnitude of the first input signal is greater than the magnitude of the second input signal.

12. The digital device of claim 7 wherein the output node is further coupled to an output conditioning circuit that includes a plurality of inverters coupled in series and operable to incrementally condition the output signal.

13. A method of buffering an output signal comprising:

receiving a first input signal at a first input node;

receiving a second input signal at a second input node, the second input signal maintaining a constant voltage level;

generating the output signal responsive to receiving the first input signal as the first input signal transitions;

mimicking the transition of the first input signal in the opposite direction at the second input node; and

generating the output signal at a faster rate responsive to the first input signal transitioning and mimicking the transition of the first input signal in the opposite direction at the second input node.

14. The method of claim 13 further comprising generating the output signal responsive to receiving the first input signal as the first input signal transitions.

15. The method of claim 14 wherein generating the output signal comprises generating a logic “

0”

output signal when the magnitude of the first input signal is greater than the voltage level of the second input signal and generating a logic “

1”

output when the magnitude of the first input signal is less than the voltage level of the second input signal.

16. The method of claim 13 wherein the output signal is conditioned by an output circuit to generate a conditioned output signal.