Anti-fuse latch self-test circuit and method

• US 7,859,925 B1
• Filed: 03/21/2007
• Issued: 12/28/2010
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Stansell, Galen E.
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US11/726,525
• Time in Patent Office: 1,378 Days
• Field of Search: 365/156, 365/154, 365/189.05, 365/201, 365/225.7
• US Class Current: 365/201
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses

Abstract

A programmable latch circuit (200) can include a volatile latch (206) that may regenerate a value determined by programmable section (202). In a test operation, a variable current source (216′) can generate a current (IBASE) that can be mirrored in test sections (252-0 and 252-1) and compared to a current drawn by either programmable element (210-0) or (210-1) by a latching operation of volatile latch (206). Variable current source (216′) can enable characterization of programmable elements (210-0 or 210-1) as well as adjustable test threshold limits. A program voltage (Vprog) applied to programmable elements (210-0 or 210-1) can be also be variable to allow for characterization of programmable elements (210-0 and 210-1) over a range of voltages.

Claims

1. A programmable latch circuit, comprising:

a volatile latch circuit that latches a data value according to a potential difference between a first data node and a second data node;

an anti-fuse circuit that includes a first anti-fuse structure coupled between a program node and the first data node, and a second anti-fuse structure coupled between the program node and the second data node; and

a test circuit that includes at least a first test current path coupled to the first node that provides a first test current to the first node in response to a first test signal, and a controllable current source that establishes the magnitude of the first test current.

2. The programmable latch circuit of claim 1, wherein:

the first test current path includes a first current source coupled in series with a first switch circuit, the first switch circuit being enabled in response to the first test signal.

3. The programmable latch circuit of claim 2, wherein:

the first current source comprises a first source transistor; and

the first switch circuit comprises a first switch transistor having a gate coupled to the first test signal.

4. The programmable latch circuit of claim 1, wherein:

the test circuit further includes a second test current path coupled to the second node that provides a second test current to the second node in response to a second test signal, the controllable current source establishing the magnitude of the second test current.

5. The programmable latch circuit of claim 4, wherein:

the second test current path includes a second current source coupled in series with a second switch circuit, the second switch circuit being enabled in response to the second test signal.

6. The programmable latch circuit of claim 5, wherein:

the second current source comprises a second source transistor; and

the second switch circuit comprises a second switch transistor having a gate coupled to the second test signal.

7. The programmable latch circuit of claim 1, wherein:

the test circuit further comprises

a first current supply transistor having a source-drain path coupled between a first supply voltage node and the first node, the first current supply transistor providing the first test current to the first node,

a bias transistor having a source-drain path coupled between the first supply voltage node and the controllable current source, the gate of the bias transistor being coupled to its drain and to the gate of the first current supply transistor.

8. The programmable latch circuit of claim 7, wherein:

the test circuit further comprises a second current supply transistor having a source-drain path coupled between the first supply voltage node and the second node and a gate coupled to the gate of the bias transistor, the second current supply transistor providing a second test current to the second node.

9. A programmable latch circuit, comprising:

a volatile latch circuit comprising a pair of latch transistors cross-coupled between a first data node and a second data node and formed in an integrated circuit substrate;

at least a pair of anti-fuse structures coupled between a program voltage node and the first data node and the second data node; and

at least one variable current source formed in the integrated circuit substrate that controls a magnitude of a first test current provided to the first data node and a magnitude of a second test current provided to the second data node.

10. The programmable latch circuit of claim 9, wherein:

the variable current source comprises a current digital-to-analog converter (DAC).

11. The programmable latch circuit of claim 10, further including:

a plurality of current set registers coupled to a digital input of the current DAC.

12. The programmable latch circuit of claim 11, wherein:

the current set registers are arranged as serial registers.

13. The programmable latch circuit of claim 9, wherein:

at least one of the data nodes of the volatile latch circuit is coupled to a test output register.

14. The programmable latch circuit of claim 9, further including:

a test circuit that includes

a mirror transistor having a gate and drain coupled to the variable current source,

a first test transistor having a source-drain path coupled to the first data node and a gate coupled to the gate of the mirror transistor, and

a second test transistor having a source-drain path coupled to the second data node and a gate coupled to the gate of the mirror transistor.

15. A method of testing antifuse devices of a programmable latch circuit, comprising the steps of:

generating a programmed current according to the state of at least one antifuse device of the programmable latch circuit, the programmed current flowing through one storage node of a volatile latch circuit;

generating a test current with a variable current source formed in the same substrate as the programmable latch circuit, the test current flowing through a different storage node of the volatile latch circuit; and

latching a test data value based on a potential difference between the one storage node and the different storage node of the volatile latch circuit.

16. The method of claim 15, wherein:

generating the programmed current includes

applying a potential at a first terminal of the antifuse device, and

enabling a current path between a second terminal of the antifuse device and the one storage node.

17. The method of claim 15, wherein:

generating the test current includes

receiving a current select value, and

adjusting the test current in response to the current select value.

18. The method of claim 15, further including:

applying a programming voltage to one of at least two antifuse devices in a programming operation to program the one antifuse device;

generating the programmed current according to the one programmed antifuse device.

19. The method of claim 18, wherein:

varying the programming voltage between a plurality of values;

generating a test current with the variable current source for each programming voltage; and

latching a test data value for each programming voltage.

20. The method of claim 15, further including:

outputting the latched data value to a test register; and

outputting the data value from the test register via an external connection of an integrated circuit device containing the programmable latch circuit.