Clock synchronization using a weighted least squares error filtering technique

• US 7,860,205 B1
• Filed: 04/12/2006
• Issued: 12/28/2010
• Est. Priority Date: 09/18/2001
• Status: Expired due to Fees

• Current Assignee: Ciena Corporation
• Original Assignee: Ciena Corporation
• Inventors: Ouellette, Michel, Aweya, James, Felske, Kent, Montuno, Delfin Y.
• Primary Examiner(s): Pathak; Sudhanshu C
• Application Number:
  US11/279,410
• Time in Patent Office: 1,721 Days
• Field of Search: 375/327, 375/343, 375/376, 375/371, 375/147, 375/324, 713/400, 370/497
• US Class Current: 375/376
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0664 unidirectional timestamps
• CPC Class Codes: H04N 21/242 Synchronization processes, e.g. processing of PCR [Program Clock References] arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/64322 IP
• CPC Class Codes: H04N 21/8547 involving timestamps for synchronizing content

Abstract

A timestamp-based clock synchronization technique is employed for CES in packet networks. The technique is based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behavior of clock synchronization errors between a transmitter and a receiver. The technique is particularly suitable for clock synchronization in networks where the transmitter and receiver are not driven from a common timing reference but the receiver requires timing reference traceable to the transmitter clock.

Claims

1. An apparatus for synchronizing a local clock at a receiver with a local clock at a transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps, the apparatus comprising:

a phase detector operable to compute an error signal indicative of differences between the timestamps and a local clock signal;

a loop filter operable to estimate a frequency offset of the receiver clock with respect to the transmitter clock by weighted least-squares calculation, and thereby produce an estimate of the receiver frequency, the weighted least-squares calculation including calculating a first order finite difference function of a past frequency estimate and an offset value, the offset value based on first and second order finite difference equations;

a control signal produced by scaling an estimated frequency by a factor dependent on a receiver oscillator characteristics;

a digital oscillator operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal; and

a counter operable to receive the digital oscillator output signal and to count pulses in the digital oscillator output signal, and output the local clock signal.

2. The apparatus of claim 1, wherein the weighted least squares calculation includes adding the frequency offset to a previous frequency estimation value.

3. The apparatus of claim 1, wherein the weighted least squares calculation includes a first order finite difference function of estimated frequency.

4. A method for synchronizing a local clock at a receiver with a clock at a transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps, the method comprising:

computing, with a phase detector, an error signal indicative of differences between the timestamps and a local clock signal;

estimating, with a loop filter, a frequency offset of the receiver clock with respect to the transmitter clock by weighted least-squares calculation, thereby producing an estimate of the receiver frequency, the weighted least-squares calculation including calculating a first order finite difference function of a past frequency estimate and an offset value, the offset value based on first and second order finite difference equations;

scaling the estimated frequency by a factor dependent on a receiver oscillator characteristics, thereby producing a control signal;

producing a digital oscillator output signal with a digital oscillator operable to oscillate at a frequency based at least in-part on the control signal; and

counting pulses in the digital oscillator output signal with a timestamp counter, thereby producing the local clock signal.

5. The method of claim 4 wherein the loop filter includes a low-pass filter.

6. The method of claim 4 wherein the digital oscillator includes a divide-by-N counter oscillator (DNCO).

7. The method of claim 6 wherein the frequency scaling factor is proportional to the frequency of the high frequency oscillator of the DNCO.

8. The method of claim 4 wherein the digital oscillator includes a direct digital synthesizer (DDS).

9. The method of claim 8 wherein the frequency scaling factor is proportional to the bit size of the DDS phase accumulator and inversely proportional to the frequency of the sampling oscillator of the DDS.

10. The method of claim 8 wherein the direct digital synthesizer includes a phase accumulator, and including the further step of generating a phase component of the local clock signal with the phase accumulator.

11. The method of claim 9 where in the direct digital synthesizer includes a mapping device, and including the further step of maintaining samples of sinusoid indexed by the output of the phase accumulator.

12. The method of claim 11 wherein the digital synthesizer includes a digital to analog converter, and including the further step of producing an analog output signal based at least in-part on the of the mapping device with the digital to analog converter.

13. The method of claim 12 wherein the digital synthesizer includes a low-pass filter, and including the further step of producing an output signal based at least in-part on the output of the digital to analog converter with the low-pass filter.

14. An apparatus for synchronizing a receiver clock to a transmitter clock based on time stamps transmitted by the transmitter, the apparatus comprising:

a phase detector to determine an error signal based on a difference between a received time stamp and a local clock signal;

a frequency estimator to estimate a frequency based on the error signal, the estimate based on a weighted least-squares calculation, the weighted least-squares calculation including calculating a first order finite difference function of a past frequency estimate and an offset value, the offset value based on first and second order finite difference equations;

a direct digital synthesizer to produce a digital oscillator output signal, the direct digital synthesizer comprising a phase accumulator to output a phase argument and a look up table to convert the phase argument to a discrete sinusoidal value; and

a counter operable to count pulses in the digital oscillator output signal and to output the local clock signal.

15. The apparatus of claim 14, further comprising an analog to digital converter, the analog to digital converter converting the discrete sinusoidal values to a sine wave approximation.

16. The apparatus of claim 15, further comprising a low pass filter, the low pass filter converting the sine wave approximation to a sine wave.

17. The apparatus of claim 14, wherein the phase accumulator has a phase resolution that divides a period of zero to 2π

into 2^q intervals, q being the number of bits of the phase accumulator output.

18. The apparatus of claim 14, wherein the phase accumulator includes a register that is clocked by a high frequency oscillator.

19. The apparatus of claim 18, wherein a frequency resolution of the phase accumulator is based on a frequency of the high frequency oscillator and a number of bits of the phase accumulator output.

20. The apparatus of claim 14, further comprising an input conditioner, the input conditioner receiving the frequency estimation and outputting a phase value to the direct digital synthesizer based on the frequency estimation.

21. The apparatus of claim 14, wherein the weighted least squares calculation includes a single exponential filtering function.