Method and apparatus for simultaneous recording and displaying two different video programs

• US 7,860,375 B2
• Filed: 03/08/2001
• Issued: 12/28/2010
• Est. Priority Date: 03/17/2000
• Status: Active Grant

• Current Assignee: InterDigital Madison Patent Holdings (InterDigital, Inc.)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Carlsgaard, Eric Stephen, Horlander, Thomas Edward
• Primary Examiner(s): Tran; Thai
• Assistant Examiner(s): Zhao; Daquan
• Application Number:
  US10/204,729
• Publication Number:
  US 20030223731A1
• Time in Patent Office: 3,582 Days
• Field of Search: 348/564, 348/565, 348/555, 386/1, 386/46, 386/95, 386125-126, 386/201, 386/239, 386/336, 386/332
• US Class Current: 386/201
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/4334 Recording operations recording of a television signal H04N5/76; arrangements for recording or accumulating broadcast information or broadcast-related information H04H60/27
• CPC Class Codes: H04N 21/440263 by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4621 Controlling the complexity of the content stream or additional data, e.g. lowering the resolution or bit-rate of the video stream for a mobile client with a small screen arrangements for using the results of monitoring on user's side in broadcast systems H04H60/65; flow control in packet networks H04L47/10
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/76 Television signal recording
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit, a second channel processing circuit, and common circuitry. The common circuit comprises a digital video decoder pipe that decodes both first and second encoded video signals. A PIP picture is produced using a common reference clock that is derived from the first video signal. In a record mode, a second channel clock reference is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms a PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.

Claims

1. A method of simultaneously recording and viewing a plurality of video signals comprising the steps of:

(a) decoding, using a first clock reference signal, a first video signal from a first video source in a common shared video decoder pipe;

(b) decoding, using said first clock reference signal, a second video signal from a second video source in the common shared video decoder pipe when said first and second video signals are to be displayed as a main picture and a picture in picture (PIP) picture;

c) encoding, using a second clock reference signal, said second video signal when said first video signal is to be displayed and said second video signal is to be recorded.

2. The method of claim 1 wherein said step (c) further comprises displaying said second video signal while recording said second video signal, as a PIP picture.

3. The method of claim 1 wherein said video decoder pipe decodes moving pictures expert group (MPEG) encoded video signals.

4. The method of claim 1 wherein the second clock reference signal is derived from the first clock reference signal.

5. The method of claim 1, wherein said first video signal and said second video signal have different decoding rates and a clock of one of said first video signal and said second a video signal having the faster decode rate is used as the first clock reference signal.

6. Apparatus for simultaneously recording and displaying a plurality of video signals comprising:

a common shared video decoder pipe for decoding said plurality of video signals from different video sources using a first clock reference signal;

a main channel processing circuit, coupled to said common shared video decoder pipe, for producing a main picture from a first of said plurality of video signals for display;

a second channel processing circuit, coupled to said common shared video decoder pipe, for producing a decoded video signal from a second of said plurality of video signals for PIP display and for encoding said second of said plurality of video signals using a second clock reference signal for recording.

7. The apparatus of claim 6 further comprising:

a reference clock generator coupled to said main channel processing circuit and said second channel processing circuit; and

a channel clock generator coupled to said second channel processing circuit.

8. The apparatus of claim 7 wherein said second channel clock generator derives a channel clock signal from a reference clock signal generated by said reference clock generator.

9. The apparatus of claim 6 wherein said second channel processing circuit comprises a digital encoder for producing an analog signal for recording.

10. The apparatus of claim 9 wherein said digital encoder produces an internal vertical synchronization signal.

11. The apparatus of claim 6, wherein said apparatus is contained within a video receiver.

12. The apparatus of claim 6, wherein said apparatus is contained within a video processing device.