Adaptive radio transceiver with a power amplifier

• US 7,860,454 B2
• Filed: 01/06/2004
• Issued: 12/28/2010
• Est. Priority Date: 10/21/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Moloudi, Shervin
• Primary Examiner(s): Ly; Nghi H
• Application Number:
  US10/752,191
• Publication Number:
  US 20040166803A1
• Time in Patent Office: 2,548 Days
• Field of Search: 455/341, 455/253.2, 455/144, 455/194.2, 455/311, 455/20, 455/323, 455/326, 455/333, 330/300, 330/311
• US Class Current: 455/20
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 2011/0494 Complex filters
• CPC Class Codes: H03H 21/0001 Analogue adaptive filters
• CPC Class Codes: H03H 21/0012 Digital adaptive filters
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H04B 17/104 of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/19 Self-testing arrangements

Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. An apparatus that amplifies a differential radio frequency signal comprising:

an integrated circuit chip, the integrated circuit chip comprising;

a first differential amplification stage comprising first cascoded MOS transistors that receive the differential radio frequency signal and produce a first stage amplified differential radio frequency signal;

a first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the first stage amplified differential radio frequency signal therethrough; and

a second differential driving stage comprising second cascoded MOS transistors that receive the first stage amplified differential radio frequency signal from the first level shift stage and produce a second stage amplified differential radio frequency signal.

2. An apparatus according to claim 1 wherein each driving stage of the second differential driving stage comprises:

a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal; and

a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor.

3. An apparatus according to claim 1 further comprising:

a second stage comprising second blocking capacitors and second shunt impedances that allow for transfer of the second stage amplified differential radio frequency signal therethrough; and

a third differential stage comprising third cascoded MOS transistors that receive the second stage amplified differential radio frequency signal from the second level shift stage and produce a third stage amplified differential radio frequency signal.

4. An apparatus according to claim 3 wherein each driving stage of the third differential driving stage comprises:

a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal; and

a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor.

5. An apparatus according to claim 1 wherein the first cascoded MOS transistors comprise a first set of MOS transistors having a common gate node and a second set of MOS transistors having a common source node.

6. An apparatus according to claim 1 wherein the second cascoded MOS transistors comprise a first set of MOS transistors having a common gate node and a second set of MOS transistors having a common source node.

7. An apparatus according to claim 1 wherein the first shunt impedances comprise resistances.

8. An apparatus according to claim 3 wherein the third cascoded MOS transistors comprise a first set of MOS transistors having a common gate node and a second set of MOS transistors having a common source node.

9. An apparatus according to claim 1 further comprising:

a second stage comprising second blocking capacitors and second shunt impedances that allow for transfer of the second stage amplified differential radio frequency signal therethrough; and

a third differential stage comprising a differential pair of MOS transistors that receive the second stage amplified differential radio frequency signal from the second level shift stage and produce a third stage amplified differential radio frequency signal.

10. An apparatus that amplifies a differential radio frequency signal, comprising:

an integrated circuit chip, the integrated circuit chip comprising;

a first differential amplification stage comprising a first set of MOS transistors having a first common gate node and a second set of MOS transistors having a second common source node, the first differential amplification stage receiving the differential radio frequency signal and producing a first stage amplified differential radio frequency signal,

a first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the first stage amplified differential radio frequency signal therethrough, and

a second differential driving stage comprising a third set of MOS transistors having a second common gate node and a fourth set of MOS transistors having a second common source node, the second differential amplification stage receiving the first stage amplified differential radio frequency signal from the first stage and producing a second stage amplified differential radio frequency signal.

11. The apparatus according to claim 10, further comprising:

a second stage comprising second blocking capacitors and second shunt impedances that allow for transfer of the second stage amplified differential radio frequency signal therethrough; and

a third differential driving stage comprising a fifth set of MOS transistors having a third common gate node and a sixth set of MOS transistors having a third common source node, the third differential amplification stage receiving the second stage amplified differential radio frequency signal from the second stage and producing a third stage amplified differential radio frequency signal.

12. The apparatus according to claim 10, further comprising:

a second stage comprising second blocking capacitors and second shunt impedances that allow for transfer of the second stage amplified differential radio frequency signal therethrough; and

a third differential driving stage comprising a fifth set of MOS transistors having a third common source node, the third differential amplification stage receiving the second stage amplified differential radio frequency signal from the second stage and producing a third stage amplified differential radio frequency signal.

13. A power amplifier on an integrated circuit chip, comprising:

a first amplification stage comprising a first set of transistors and a second set of transistors, the first set of transistors sharing a first gate node coupled to a voltage supply, the second set of transistors sharing a first source node, the first amplification stage receiving a differential wireless communication signal and producing a first amplification stage differential wireless communication signal;

a first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the first amplification stage differential wireless communication signal therethrough; and

a second amplification stage comprising a third set of transistors sharing a second source node, the second stage receiving the first amplification stage differential wireless communication signal and producing a second amplification stage differential wireless communication signal.

14. The power amplifier according to claim 13, wherein the first source node is coupled to an electrical ground.

15. The power amplifier according to claim 14, wherein the first source node is coupled to the electrical ground via a current source.

16. The power amplifier according to claim 13, further comprising:

a first set of capacitors disposed between differential outputs of the first amplification stage and differential inputs of the second amplification stage.

17. The power amplifier according to claim 13, further comprising:

a first set of inductors coupled to drain nodes of the first set of transistors.

18. The power amplifier according to claim 17, further comprising:

a first set of capacitors coupled to the drain nodes of the first set of transistors, the first set of capacitors being disposed between differential outputs of the first amplification stage and differential inputs of the second amplification stage.

19. The power amplifier according to claim 18, wherein at least one of the first set of transistors, the second set of transistors, the third set of transistors comprises one or more MOS transistors.

20. The power amplifier according to claim 19, wherein the one or more MOS transistors comprise at least two MOS transistors arranged in a CMOS configuration.

21. The power amplifier according to claim 19, wherein the one or more MOS transistors comprise at least two MOS transistors arranged in a cascode configuration.

22. The power amplifier according to claim 13, wherein the second set of transistors comprises a differential pair.

23. The power amplifier according to claim 13, wherein the third set of transistors comprises a differential pair.

24. The power amplifier according to claim 13, wherein the first amplification stage and the second amplification stage are part of a differential power amplifier.

25. The power amplifier according to claim 13, wherein the first amplification stage and the second amplification stage are part of a quadrature power amplifier.

26. The power amplifier according to claim 13, wherein the first amplification stage and the second amplification stage are part of a programmable power amplifier.

27. The power amplifier according to claim 13, wherein the differential wireless communication signal is at least one of a local area network communication signal, a personal area network communication signal and a wireless communication signal in compliance with IEEE 802.11.

28. The power amplifier according to claim 13, wherein the wireless communication signal is a radio frequency communication signal.

29. The power amplifier according to claim 13, wherein the wireless communication signal is a spread spectrum communication signal.

30. The power amplifier according to claim 13, wherein the first amplification stage and the second amplification stage are part of a programmable wireless communication transmitter.

31. The power amplifier according to claim 30, wherein the programmable wireless communication transmitter is an integrated circuit.

32. The power amplifier according to claim 13, wherein the first amplification stage and the second amplification stage are part of a programmable wireless communication transceiver.

33. The power amplifier according to claim 32, wherein the programmable wireless communication transceiver is an integrated circuit.

34. The power amplifier according to claim 13, wherein the integrated circuit chip is part of an integrated radio transceiver.

35. The power amplifier according to claim 34, wherein the integrated radio transceiver comprises a heterodyne complex circuit architecture.

36. A method for amplifying a radio frequency communication signal on an integrated transceiver circuit chip, comprising:

amplifying a radio frequency communication signal in a first amplification stage comprising a first differential pair of transistors, the first differential pair sharing a first common source node;

sending the radio frequency communication signal amplified by the first amplification stage through a first stage, the first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the radio frequency communication signal amplified by the first amplification stage therethrough; and

amplifying the radio frequency communication signal sent through the first stage in a second amplification stage, the second amplification stage comprising a second differential pair of transistors, the second differential pair sharing a second common source node.

37. The method according to claim 36, wherein the radio frequency communication signal is a differential signal.

38. The method according to claim 36, wherein the radio frequency communication signal is a quadrature signal.

39. The method according to claim 36, wherein the capacitor comprises a plurality of capacitors.

40. The method according to claim 36, wherein the sending of the radio frequency communication signal amplified by the first amplification stage comprises sending the radio frequency communication signal amplified by the first amplification stage through the capacitor of the first stage.

41. The method according to claim 36, wherein the impedance comprises a shunt impedance.

42. The method according to claim 36, wherein the impedance comprises a resistance.

43. The method according to claim 36, wherein the first differential pair is part of a cascode configuration of transistors.

44. The method according to claim 36, wherein the first common source is coupled to a DC voltage reference or an electrical ground.

45. A method for amplifying a radio frequency communication signal on an integrated transceiver circuit chip of a wireless communication device, comprising:

amplifying a radio frequency communication signal in a first amplification stage comprising a first differential pair of transistors, the first differential pair sharing a first common source node;

sending the radio frequency communication signal amplified by the first amplification stage through a first stage, the first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the radio frequency communication signal amplified by the first amplification stage therethrough; and

amplifying the radio frequency communication signal amplified in the first amplification stage, the second amplification stage comprising a second differential pair of transistors, the second differential pair sharing a second common source node,

wherein the wireless communication device supports spread spectrum modulation or orthogonal frequency division multiplexing.

46. The method according to claim 45, wherein the radio frequency communication signal is a differential signal.

47. The method according to claim 45, wherein the radio frequency communication signal is a quadrature signal.

48. The method according to claim 45, wherein the first differential pair is a part of a cascode configuration of transistors.

49. The method according to claim 48, wherein the cascode configuration of transistors comprises CMOS transistors.

50. The method according to claim 45, wherein the second differential pair is part of a cascode configuration of transistors.

51. The method according to claim 45, wherein the second amplification stage comprises a pair of transistors coupled to the second differential pair, the pair of transistors sharing a common gate node.

52. A radio frequency transceiver of a wireless communication device, comprising:

an integrated circuit chip, the integrated circuit chip comprising;

a differential first amplification stage comprising first cascoded MOS transistors that receive the differential radio frequency signal and produce a first stage amplified differential radio frequency signal, the differential first amplification stage being supplied with a predetermined first supply voltage;

a first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the first stage amplified differential radio frequency signal therethrough; and

a differential second amplification stage comprising second cascoded MOS transistors that receive the first stage amplified differential radio frequency signal from the first amplification stage and produce a second stage amplified differential radio frequency signal, the differential second amplification stage being supplied with a predetermined second supply voltage that is greater than the first supply voltage,

wherein the wireless communication device supports direct sequence spread spectrum modulation or orthogonal frequency division multiplexing.

53. An apparatus that amplifies a differential radio frequency signal in a transmitter of a wireless communication device, comprising:

an integrated circuit chip, the integrated circuit chip comprising;

a differential first amplification stage including first cascoded MOS transistors that receive the differential radio frequency signal and produce a first stage amplified differential radio frequency signal, the differential first amplification stage being supplied with a first supply voltage;

a first stage comprising first blocking capacitors and first shunt impedances that allow for transfer of the first stage amplified differential radio frequency signal therethrough; and

a differential second amplification stage that receives the first stage amplified differential radio frequency signal from the first amplification stage and produces a second stage amplified differential radio frequency signal, the differential second amplification stage being supplied with a second supply voltage that is greater than the first supply voltage,

wherein the wireless communication device supports spread spectrum modulation or orthogonal frequency division multiplexing.

54. The apparatus according to claim 53, wherein the differential second amplification stage comprises a differential pair of MOS transistors.

55. The apparatus according to claim 53, wherein the first supply voltage comprises a predetermined supply voltage.

56. The apparatus according to claim 53, wherein the second supply voltage comprises a predetermined supply voltage.