Network processor system including a central processor and at least one peripheral processor

• US 7,860,967 B2
• Filed: 01/10/2006
• Issued: 12/28/2010
• Est. Priority Date: 12/22/1999
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Ross, Mark A., Petersen, Brian A.
• Primary Examiner(s): Srivastava; Vivek
• Assistant Examiner(s): Pollack; Melvin H
• Application Number:
  US11/328,655
• Publication Number:
  US 20060117088A1
• Time in Patent Office: 1,813 Days
• Field of Search: 709/223, 709/224, 709/230, 709/246, 370/389, 370392-394
• US Class Current: 709/224
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: Y10S 707/99933 Query processing, i.e. searching

Abstract

The present invention consists of a general purpose, software-controlled central processor (CP) augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, which provides the central processor with a numerical summary of the packet format; a packet deconstructor, which extracts designated fields from the packet the positions of which are determined by the central processor according to the packet format; a search engine, which is supplied a lookup index by and returns its results to the central processor; and a packet editor which modifies the packet as determined by the central processor using (in part) information returned from other peripherals. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability: rather than having to modify a circuit or system design in an ASIC or other hardware, new packet processing applications may be accommodated through the development of new software and its deployment in the central and/or peripheral processors.

Claims

1. An apparatus comprising:

a first peripheral processor, wherein

said first peripheral processor is configured to perform a first packet processing task,

said first packet processing task is at least one packet processing task of a set of a packet processing tasks, and

each packet processing task of said set of packet processing tasks is one of

packet parsing,

packet deconstruction,

packet searching, and

packet editing;

a second peripheral processor, wherein

said second peripheral processor is configured to perform a second packet processing task,

said second packet processing task is one of a plurality of packet processing tasks, and

said plurality of packet processing tasks comprises said each packet processing task of said set of packet processing tasks; and

a central processor configured to

receive a packet, wherein

said packet comprises information,

process said packet by virtue of being configured to

cause said first peripheral processor to perform said first packet processing task, wherein

said first packet processing task is performed using said information,

determine said second packet processing task by virtue of being configured to evaluate a result of said first packet processing task, and

cause said second peripheral processor to perform said second packet processing task.

2. The apparatus of claim 1, wherein

said first and said second peripheral processors are configured to perform each of said plurality of said packet processing tasks.

3. The apparatus of claim 1, further comprising:

a plurality of peripheral processors, wherein

said plurality of peripheral processors comprise said first and said second peripheral processors,

and

each of said plurality of peripheral processors is configured to perform one of said packet processing tasks.

4. The apparatus of claim 3, wherein

said central processor and said plurality of peripheral processors are configured to perform certain ones of said packet processing tasks sequentially and certain others of said packet processing tasks in parallel.

5. The apparatus of claim 3, wherein

said central processor is coupled to control said plurality of peripheral processors,

said central processor is configured to cause each of said plurality of peripheral processors to perform at least one of said at least one of said packet processing tasks, and

said central processor and said plurality of peripheral processors are configured to communicate with one another.

6. The apparatus of claim 5, wherein

said plurality of peripheral processors comprise at least one of a packet parsing processor, a packet deconstruction processor, a search engine processor and a packet editing processor.

7. The apparatus of claim 6, wherein

said packet editing processor is configured to modify routing information in a header of said packet using information provided by at least one of said packet parsing processor, said packet deconstruction processor and said search engine processor.

8. The apparatus of claim 5, wherein

said plurality of peripheral processors comprise a packet parsing processor, and

said packet parsing processor is configured to generate a numerical summary of said packet.

9. The apparatus of claim 8, wherein

said central processor is further configured to cause said packet parsing processor to perform said generating, and

said packet parsing processor is configured to provide said numerical summary to said central processor.

10. The apparatus of claim 5, wherein

said plurality of peripheral processors comprise a packet deconstruction processor, and

said packet deconstruction processor is configured to extract a field from said packet.

11. The apparatus of claim 10, wherein

said central processor is further configured to designate said field to communicate said designation to said packet deconstruction processor.

12. The apparatus of claim 5, wherein

said plurality of peripheral processors comprise a search engine processor, and

said search engine processor is configured to identify network information associated with said packet.

13. The apparatus of claim 12, wherein

said search engine processor is configured to perform said identification by virtue of being configured to determine routing information by virtue of being configured to perform a lookup operation in a routing information table.

14. The apparatus of claim 5, wherein

said plurality of peripheral processors comprise a packet editing processor, and

said packet editing processor is configured to modify information in said packet.

15. The apparatus of claim 14, wherein

said packet editing processor is configured to perform said modification by virtue of being configured to modify routing information in a header of said packet.

16. A method comprising:

receiving a packet by a central processor, wherein

said packet comprises information; and

processing said packet by performing a plurality of packet processing tasks, wherein

said processing comprises

causing a first peripheral processor to perform a first packet processing task on said packet, wherein

said first packet processing is performed using said information,

said first packet processing task is at least one packet processing task of a set of packet processing tasks,

each packet processing task of said set of packet processing tasks is one of

 

packet parsing,

 

packet deconstruction,

 

packet searching, and

 

packet editing,

determining a second packet processing task by causing said central processor to evaluate a result of said first packet processing task, and

causing a second peripheral processor to perform said second packet processing task on said packet, wherein

said second packet processing task is one of a plurality of packet processing tasks, and

said plurality of packet processing tasks comprises said each packet processing task of said set of packet processing tasks.

17. The method of claim 16, wherein said first peripheral processor is one of a plurality of peripheral processors, and said packet processing tasks comprise at least one of:

packet deconstruction, wherein said packet deconstruction comprises deconstructing said packet header to form header data;

packet searching, wherein said packet searching comprises searching one or more data structures based on said header data to produce search results; and

packet editing, wherein said packet editing comprises editing said packet based on said search results, said header data, and said vector, wherein each of said deconstructing, said searching and said editing are performed by a corresponding one of said peripheral processors.

18. The method of claim 17, wherein said processing further comprises:

monitoring said deconstructing, said searching, and said editing, and

causing said first and said second peripheral processors to share information regarding said packet among one another.

19. The method of claim 17, wherein:

said deconstructing further comprises forming a search argument;

said processing further comprises operating on said search argument to form a modified search argument prior to said searching; and

said searching uses said modified search argument.

20. An apparatus comprising:

a first peripheral processor, wherein

said first peripheral processor is configured to perform a first packet processing task,

said first packet processing task is at least one packet processing task of a set of a packet processing tasks, and

each packet processing task of said set of packet processing tasks is one of

packet parsing,

packet deconstruction,

packet searching, and

packet editing;

a second peripheral processor, wherein

said second peripheral processor is configured to perform a second packet processing task,

said second packet processing task is one of a plurality of packet processing tasks, and

said plurality of packet processing tasks comprises said each packet processing task of said set of packet processing tasks;

a central processor, coupled to control said first and said second peripheral processors, wherein

the central processor is configured to receive a packet, and

said packet comprises information; and

means for processing said packet, wherein

said means for processing comprises

means for causing said central processor to coordinate said packet processing tasks between said first and said second peripheral processors,

means for causing said first peripheral processor to perform said first packet processing task on said packet, wherein

said first packet processing task is performed using said information

means for causing said central processor to determine a second packet processing task of said packet processing tasks comprising

means for evaluating a result of said first packet processing task, and

means for causing said second peripheral processor to perform said second packet processing task on said packet.