Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory

• US 7,861,058 B2
• Filed: 04/27/2007
• Issued: 12/28/2010
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Jeday, Adrian, Bosch, Derek, Fruin, Matt, Yang, Chia, Moore, Christopher S.
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US11/796,828
• Publication Number:
  US 20070208907A1
• Time in Patent Office: 1,341 Days
• Field of Search: 711/100, 711/103, 711/118, 711/154, 711/200, 711/202, 711/206, 711/3
• US Class Current: 711/206
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2142 using write-once memory, e.g. OTPROM
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/08 from or to individual record carriers, e.g. punched card , memory card, integrated circuit [IC] card or smart card

Abstract

The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash—an erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a viable way to bridge one-time or few-time programmable memories with existing consumer electronic devices that have flash card slots. These embodiments also allow future consumer electronic devices to be designed without updating firmware to include a file system customized for a one-time or few-time programmable memory.

Claims

1. A memory device comprising:

a memory array, wherein the memory array is organized into logical units, wherein each logical unit is associated with a sideband area and wherein each logical unit can be partially written into, whereby multiple write operations can be performed to each logical unit before the logic unit is full; and

a controller in communication with the memory array, wherein the controller is operative to;

(a) receive a request from a host device in communication with the memory device to write data to a first address in the memory array;

(b) write the data to a second address instead of the first address;

(c) update a file system structure in the memory array to indicate that the second address is no longer free; and

(d) write either the second address or an address to a remap table in a sideband area of the first address;

wherein the controller is further operative to write ECC data in a sideband area for a logical unit when a last write operation is made to the logical unit.

2. The memory device of claim 1, wherein the controller is operative to write ECC data in a sideband area for a logical unit only when a last write operation is made to the logical unit.

3. The memory device of claim 1, wherein the controller is operative to write ECC data for a logical unit in a sideband area both when a first write operation is made to the logical unit and when a last write operation is made to the logical unit.

4. The memory device of claim 1, wherein the controller is operative to write ECC data in a sideband area for a logical unit when a last two bytes are written to the logical unit.

5. The memory device of claim 1, wherein the controller is operative to write ECC data in a sideband area for a logical unit when a last six bytes are written to the logical unit.

6. The memory device of claim 1, wherein the controller is further operative to perform a remap operation in response to an ECC word being invalid.

7. The memory device of claim 1, wherein the memory array comprises a one-time programmable memory array.

8. The memory device of claim 1, wherein the memory array comprises a few-time programmable memory array.

9. The memory device of claim 1, wherein the memory array comprises a three-dimensional memory array.