Semiconductor die separation method

• US 7,863,159 B2
• Filed: 11/25/2008
• Issued: 01/04/2011
• Est. Priority Date: 06/19/2008
• Status: Expired due to Fees

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Vertical Circuits LLC
• Inventors: Co, Reynaldo, Melcher, DeAnn Eileen, Pan, Weiping, Villavicencio, Grant
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US12/323,288
• Publication Number:
  US 20090315174A1
• Time in Patent Office: 770 Days
• Field of Search: 438/460, 438/462, 438/465, 257/E21.599, 257/E21.602, 257/E21.603
• US Class Current: 438/460
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

Claims

1. A method for preparing singulated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof, the wafer having a thickness greater than a prescribed die thickness;

performing a first wafer cutting procedure, wherein cuts are made along a first set of streets from the front side to a depth at least as great as the prescribed die thickness;

carrying out a die preparation procedure;

thinning the wafer to the prescribed die thickness; and

performing a second wafer cutting procedure along a second set of streets, passing completely through the wafer.

2. The method of claim 1, wherein the first wafer cutting procedure further comprises making cuts along the second set of streets to a depth less than the prescribed die thickness.

3. The method of claim 2 wherein the first wafer cutting procedure defines die edges, and die sidewalls.

4. The method of claim 1 wherein the first wafer cutting procedure defines die edges and die sidewalls.

5. The method of claim 1 wherein the first set of streets includes streets fronted by interconnect die edges, and wherein the first wafer cutting procedure defines interconnect edges and interconnect sidewalls.

6. The method of claim 5 wherein the die preparation procedure includes applying an electrical insulation onto at least the interconnect edges.

7. The method of claim 5 wherein the die preparation procedure includes applying an electrical insulation onto at least the interconnect sidewalls.

8. The method of claim 1 wherein the die preparation procedure includes applying an electrical insulation onto a wafer surface.

9. The method of claim 1 wherein thinning the wafer results in an array of separate strips of connected die.

10. The method of claim 1 wherein thinning the wafer results in an array of separate blocks of connected die.

11. The method of claim 1, further comprising applying an electrically insulating layer onto a backside of the thinned wafer.

12. The method of claim 1 wherein thinning the wafer is carried out prior to performing the second wafer cutting procedure.

13. The method of claim 1 wherein performing the second wafer cutting procedure is carried out prior to thinning the wafer.

14. A method for preparing singulated semiconductor die, comprising

providing a wafer having a front side in which semiconductor chip active regions are formed, the active regions being bounded by saw streets, the active regions having interconnect pads arranged in an interconnect margin along an interconnect edge thereof;

thinning the wafer to a prescribed die thickness;

performing a first wafer cutting procedure, wherein cuts are made along a first set of streets from the front side to a depth at least as great as the prescribed die thickness;

carrying out a die preparation procedure; and

performing a second wafer cutting procedure along a second set of streets, passing completely through the thinned wafer.

15. The method of claim 14, wherein the first wafer cutting procedure further comprises making cuts along the second set of streets to a depth less than the prescribed die thickness.

16. The method of claim 15 wherein the first wafer cutting procedure defines die edges and die sidewalls.

17. The method of claim 14 wherein the first wafer cutting procedure defines die edges and die sidewalls.

18. The method of claim 14 wherein the first set of streets includes streets fronted by interconnect die edges, and wherein the first cutting procedure defines interconnect edges and interconnect sidewalls.

19. The method of claim 18 wherein the die preparation procedure includes applying an electrical insulation onto at least the interconnect edges.

20. The method of claim 18 wherein the die preparation procedure includes applying an electrical insulation onto at least the interconnect sidewalls.

21. The method of claim 14 wherein the die preparation procedure includes applying an electrical insulation onto a wafer surface.

22. The method of claim 14 wherein performing the first wafer cutting procedure results in an array of separate strips of connected die.

23. The method of claim 22 wherein performing the first wafer cutting procedure results in an array of separate blocks of connected die.

24. The method of claim 14, further comprising applying an electrically insulating layer onto a backside of the thinned wafer.