Thin film transistor array panel and manufacturing method thereof
First Claim
1. A thin film transistor array panel comprising:
- an insulating substrate;
a channel layer including an oxide material formed on the insulating substrate;
a gate insulating layer formed on the channel layer;
a gate electrode formed on the gate insulating layer;
an interlayer insulating layer formed on the gate electrode;
a data line formed on the interlayer insulating layer, the data line including a source electrode, wherein the data line comprises a first conductive layer and a second conductive layer formed on the first conductive layer;
a drain electrode formed on the interlayer insulating layer, the drain electrode including the first conductive layer and the second conductive layer formed on the first conductive layer;
a pixel electrode comprising the first conductive layer; and
a passivation layer formed on the data line and the drain electrode.
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Accused Products
Abstract
The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
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Citations
18 Claims
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1. A thin film transistor array panel comprising:
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an insulating substrate; a channel layer including an oxide material formed on the insulating substrate; a gate insulating layer formed on the channel layer; a gate electrode formed on the gate insulating layer; an interlayer insulating layer formed on the gate electrode; a data line formed on the interlayer insulating layer, the data line including a source electrode, wherein the data line comprises a first conductive layer and a second conductive layer formed on the first conductive layer; a drain electrode formed on the interlayer insulating layer, the drain electrode including the first conductive layer and the second conductive layer formed on the first conductive layer; a pixel electrode comprising the first conductive layer; and a passivation layer formed on the data line and the drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 18)
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11. The thin film transistor array panel of claim l0, further comprising:
a storage electrode line formed on the substrate.
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15. A thin film transistor array panel comprising:
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an insulating substrate; a channel layer including an oxide material formed on the insulating substrate; a gate insulating layer formed on the channel layer; a gate line formed on the gate insulating layer; an interlayer insulating layer formed on the gate line; a data line including a source electrode and a drain electrode formed on the interlayer insulating layer; a pixel electrode formed on the interlayer insulating layer, and connected to the drain electrode; a passivation layer formed on the data line and the drain electrode; and a spacer formed on the passivation layer, wherein the passivation layer is coextensive with the data line and includes a portion covering the drain electrode, and at least a part of a boundary of the spacer is the same as a boundary of the passivation layer. - View Dependent Claims (16, 17)
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Specification