Semiconductor device and a method for manufacturing the same

• US 7,863,619 B2
• Filed: 04/21/2009
• Issued: 01/04/2011
• Est. Priority Date: 10/01/1993
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Teramoto, Satoshi, Takemura, Yasuhiko
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US12/427,139
• Publication Number:
  US 20090200611A1
• Time in Patent Office: 623 Days
• Field of Search: 257/66, 257/71, 257/72, 257/E29.273, 257/E29.276
• US Class Current: 257/66
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.

Claims

1. A semiconductor device comprising:

a single crystalline semiconductor island on an insulating surface, the single crystalline semiconductor island comprising a source region, a drain region, and a channel region located between the source region and the drain region;

a gate electrode over the channel region with an insulating layer interposed therebetween;

an impurity region having a lower impurity concentration than the source region and the drain region, the impurity region being located between the channel region and at least one of the source region and the drain region; and

a silicon nitride film over the gate electrode and the single crystalline semiconductor island,

wherein each of the source region and the drain region comprises a metal silicide region, and the silicon nitride film is in contact with an upper surface of the metal silicide region.

2. The semiconductor device according to claim 1 wherein each of the source region and the drain region is approximately coincide with the metal silicide region.

3. The semiconductor device according to claim 1 wherein the gate electrode is made of a metal.

4. The semiconductor device according to claim 1 wherein the metal silicide region is a silicide of a metal selected from the group consisting of titanium, nickel, molybdenum, tungsten, platinum and palladium.

5. The semiconductor device according to claim 1 wherein a sheet resistance of the metal silicide region is 10-50 Ω

/square and a sheet resistance of the impurity region is 10-500 kΩ

/square.

6. The semiconductor device according to claim 1 wherein the silicon nitride film is 200-2000 Å

thick.

7. The semiconductor device according to claim 1 wherein the insulating surface is a surface of a silicon oxide film formed on a silicon wafer.

8. A semiconductor device comprising:

a single crystalline semiconductor island on an insulating surface, the single crystalline semiconductor island comprising a source region, a drain region, and a channel region located between the source region and the drain region;

a gate electrode over the channel region;

an impurity region having a lower impurity concentration than the source region and the drain region, the impurity region being located between the channel region and at least one of the source region and the drain region;

an insulating film comprising silicon oxide on and in contact with the impurity region; and

a silicon nitride film over the gate electrode and the single crystalline semiconductor island,

wherein each of the source region and the drain region comprises a metal silicide region, and the silicon nitride film is in contact with an upper surface of the metal silicide region.

9. The semiconductor device according to claim 8 wherein the metal silicide region is a silicide of a metal selected from the group consisting of titanium, nickel, molybdenum, tungsten, platinum and palladium.

10. The semiconductor device according to claim 8 wherein a sheet resistance of the metal silicide region is 10-50 Ω

/square and a sheet resistance of the impurity region is 10-500 kΩ

/square.

11. The semiconductor device according to claim 8 wherein the silicon nitride film is 200-2000 Å

thick.

12. The semiconductor device according to claim 8 wherein the insulating surface is a surface of a silicon oxide film formed on a silicon wafer.

13. A semiconductor device comprising:

a single crystalline semiconductor island on an insulating surface, the single crystalline semiconductor island comprising a source region, a drain region, and a channel region located between the source region and the drain region;

a gate electrode over the channel region with an insulating layer interposed therebetween;

an impurity region having a lower impurity concentration than the source region and the drain region, the impurity region being located between the channel region and at least one of the source region and the drain region;

a silicon nitride film over the gate electrode and the single crystalline semiconductor island; and

an interlayer insulating film comprising silicon oxide over the silicon nitride film,

wherein each of the source region and the drain region comprises a metal silicide region, and the silicon nitride film is in contact with an upper surface of the metal silicide region.

14. The semiconductor device according to claim 13 wherein the metal silicide region is a silicide of a metal selected from the group consisting of titanium, nickel, molybdenum, tungsten, platinum and palladium.

15. The semiconductor device according to claim 13 wherein a sheet resistance of the metal silicide region is 10-50 Ω

/square and a sheet resistance of the impurity region is 10-500 kΩ

/square.

16. The semiconductor device according to claim 13 wherein the silicon nitride film is 200-2000 Å

thick.

17. The semiconductor device according to claim 13 wherein the insulating surface is a surface of a silicon oxide film formed on a silicon wafer.

18. A semiconductor device comprising:

a single crystalline semiconductor island on an insulating surface, the single crystalline semiconductor island comprising a source region, a drain region, and a channel region located between the source region and the drain region;

a gate electrode over the channel region with an insulating layer interposed therebetween;

an impurity region having a lower impurity concentration than the source region and the drain region, the impurity region being located between the channel region and at least one of the source region and the drain region; and

a silicon nitride film over the gate electrode and the single crystalline semiconductor island,

wherein each of the source region and the drain region comprises a nickel silicide region, and the silicon nitride film is in contact with an upper surface of the nickel silicide region.

19. The semiconductor device according to claim 18 wherein each of the source region and the drain region is approximately coincide with the nickel silicide region.

20. The semiconductor device according to claim 18 wherein the gate electrode is made of a metal.

21. The semiconductor device according to claim 18 wherein the silicon nitride film is 200-2000 Å

thick.

22. The semiconductor device according to claim 18 wherein the insulating surface is a surface of a silicon oxide film formed on a silicon wafer.

23. A semiconductor device comprising:

a single crystalline semiconductor island on an insulating surface, the single crystalline semiconductor island comprising a source region, a drain region, and a channel region located between the source region and the drain region;

a gate electrode over the channel region;

an impurity region having a lower impurity concentration than the source region and the drain region, the impurity region being located between the channel region and at least one of the source region and the drain region;

an insulating film comprising silicon oxide on and in contact with the impurity region; and

a silicon nitride film over the gate electrode and the single crystalline semiconductor island,

wherein each of the source region and the drain region comprises a nickel silicide region, and the silicon nitride film is in contact with an upper surface of the nickel silicide region.

wherein the gate electrode is located over the channel region with the insulating film interposed therebetween.

24. The semiconductor device according to claim 23 wherein the silicon nitride film is 200-2000 Å

thick.

25. The semiconductor device according to claim 23 wherein the insulating surface is a surface of a silicon oxide film formed on a silicon wafer.

26. A semiconductor device comprising:

a single crystalline semiconductor island on an insulating surface, the single crystalline semiconductor island comprising a source region, a drain region, and a channel region located between the source region and the drain region;

a gate electrode over the channel region with an insulating layer interposed therebetween;

an impurity region having a lower impurity concentration than the source region and the drain region, the impurity region being located between the channel region and at least one of the source region and the drain region;

a silicon nitride film over the gate electrode and the single crystalline semiconductor island; and

an interlayer insulating film comprising silicon oxide over the silicon nitride film,

wherein each of the source region and the drain region comprises a nickel silicide region, and the silicon nitride film is in contact with an upper surface of the nickel silicide region.

27. The semiconductor device according to claim 26 wherein the silicon nitride film is 200-2000 Å

thick.

28. The semiconductor device according to claim 26 wherein the insulating surface is a surface of a silicon oxide film formed on a silicon wafer.