Semiconductor component and method for producing it

• US 7,863,680 B2
• Filed: 07/03/2008
• Issued: 01/04/2011
• Est. Priority Date: 09/10/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Kotz, Dietmar, Peri, Hermann, Zelsacher, Rudolf, Hirler, Franz, Willmeroth, Armin
• Primary Examiner(s): Dickey; Thomas L
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US12/167,437
• Publication Number:
  US 20080265318A1
• Time in Patent Office: 915 Days
• Field of Search: 257/329, 257/330, 257/334, 257/339, 257/E27.06, 257/E21.616, 257/327, 257/E29.133, 438/270
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component includes a surface region. A modified doping region is provided in the edge region of the cell array. In the surface region or modified doping region the doping concentration is lowered and/or in the surface region or modified doping region the conductivity type is formed such that it is opposite to the conductivity type of the actual semiconductor material region, or in which a field plate region is provided.

Claims

1. A semiconductor component, comprising:

a semiconductor material region comprising a semiconductor element cell array of a plurality of trench transistor semiconductor elements, said trench transistor semiconductor elements comprising source regions, body regions and trenches including gate electrodes;

wherein the semiconductor material region further comprises a two-stage epitaxial layer having a surface region at a surface of the semiconductor material region and a lower region, said surface region having a lower doping concentration relative to the lower region and having a vertical depth from the surface of the semiconductor material region that embeds or encloses the source and the body regions, but does not exceed the depth of the trenches such that the trenches extend through the surface region and into, but not beyond. the lower region of the two-stage epitaxial layer.

2. The semiconductor component of claim 1, wherein the epitaxial layer stage at the surface is largely undoped.

3. The semiconductor component of claim 1, wherein the epitaxial layer stage at the surface is at least as thick as a source and a channel region of the trench transistor semiconductor elements together.

4. The semiconductor component of claim 1, wherein the epitaxial layer stage at the surface comprises a dopant concentration below 10¹⁶ cm⁻

3.

5. The semiconductor component of claim 3, wherein a modified doping region is formed substantially in a manner patterned laterally or over the whole area.

6. A semiconductor component, comprising:

a semiconductor material region comprising a semiconductor element cell array of a plurality of trench transistor semiconductor elements, said trench transistor semiconductor elements comprising source regions, body regions and trenches including gate electrodes;

wherein the semiconductor material further comprises a sequence of a plurality of epitaxial zones including at least a surface region at a surface of the semiconductor material region and a lower region, the surface region having a lowered dopant concentration relative to the lower region, said surface region having a vertical depth from the surface of the semiconductor material region that embeds or encloses the source region and the body region, but does not exceed the depth of the trench such that the trench extends through the surface region and into, but not beyond, the lower region.

7. The semiconductor component of claim 6, wherein the epitaxial zone at the surface is largely undoped.

8. The semiconductor component of claim 6, wherein the epitaxial zone at the surface is at least as thick as a source and a channel region of the trench transistor semiconductor elements together.

9. The semiconductor component of claim 6, wherein a dopant concentration of the epitaxial zone at the surface is below 10¹⁶ cm⁻

3.

10. The semiconductor component of claim 6, wherein the epitaxial zone at the surface is a counterdoped zone including dopants of a conductivity type opposite to that of the other of the plurality of epitaxial zones.

11. A semiconductor component, comprising:

a semiconductor material region comprising;

a semiconductor element cell array of a plurality of trench transistor semiconductor elements; and

a doped epitaxial layer and a body region of a conductivity type opposite to the conductivity type of the epitaxial layer,

wherein the doped epitaxial layer comprises a counterdoped surface region including dopants of a conductivity type opposite to that of the rest of the epitaxial layer and means for lowering the effective dopant concentration of the epitaxial layer in proximity to one whole surface side of the semiconductor material region, trenches of said trench transistor semiconductor elements penetrating through said counterdoped surface region and into, but not through, a remaining portion of the doped epitaxial layer below the counterdoped surface region.

12. The semiconductor component of claim 11, wherein an effective dopant concentration of the counterdoped region is below 10¹⁶ cm⁻

3.

13. The semiconductor component of claim 11, wherein the counterdoped region is at least as thick as a source and a channel region of the trench transistor semiconductor elements together.

14. A semiconductor component, comprising:

a semiconductor material region comprising;

a semiconductor element cell array of a plurality of trench transistor semiconductor elements; and

a doped epitaxial layer and a body region of a conductivity type opposite to that of the epitaxial layer,

wherein the doped epitaxial layer further comprises a counterdoped surface region and a lower region, the counterdoped surface region limited to an edge region of the trench transistor cell array region and including dopants of a conductivity type opposite to that of the rest of the epitaxial layer and configured to lower the effective dopant concentration of the epitaxial layer, trenches of said trench transistor semiconductor elements penetrating through said surface region but only partially through the lower region.

15. The semiconductor component of claim 14, wherein the counterdoped region comprises an effective dopant concentration below 10¹⁶ cm⁻

3.

16. The semiconductor component of claim 14, wherein the counterdoped region is at least as thick as a source and a channel region of the trench transistor semiconductor elements together.

17. A method for manufacturing a trench transistor cell array, comprising:

providing a semiconductor material region by forming a two-stage epitaxial layer on a semiconductor substrate, the two-stage epitaxial layer having a surface region at a surface of the semiconductor material region and a lower region, the surface region having a lowered dopant concentration relative to the lower region; and

forming gate trenches penetrating through the surface region and into, but not beyond, the lower region of the semiconductor material region.

18. The semiconductor component of claim 17, comprising forming the epitaxial layer stage at the surface largely undoped.

19. A method for manufacturing a trench transistor cell array, comprising:

providing a semiconductor material region by forming a sequence of a plurality of epitaxial zones on a semiconductor substrate, the sequence of epitaxial zones including at least a surface region at a surface of the semiconductor material region and a lower region, the surface region having a lowered dopant concentration relative to the lower region; and

forming gate trenches penetrating through the surface region and into, but not through, the lower region of the semiconductor material region.

20. The semiconductor component of claim 19, comprising forming the epitaxial zone at the surface largely undoped.

21. A method for manufacturing a trench transistor cell array, comprising:

providing a semiconductor material region by forming a doped epitaxial layer on a semiconductor substrate;

forming a counterdoped surface region in a proximity of one whole surface side of the epitaxial layer by inserting dopants of a conductivity type opposite to that of the doped epitaxial layer; and

forming gate trenches penetrating through the counterdoped surface region and into, but not through, a remaining portion of the doped epitaxial layer below the counterdoped surface region.

22. A method for manufacturing a trench transistor cell array, comprising:

providing a semiconductor material region by forming a doped epitaxial layer on a semiconductor substrate;

forming a counterdoped surface region limited to an edge region of the trench transistor cell array by inserting dopants of a conductivity type opposite to that of the doped epitaxial layer; and

forming gate trenches penetrating through the counterdoped surface region and into, but not through, a remaining portion of the doped epitaxial layer.

23. A semiconductor component, comprising:

a semiconductor material region comprising a semiconductor element cell array of a plurality of trench transistor semiconductor elements, said trench transistor semiconductor elements comprising sourceregions, body regions and trenches including gate electrodes; and

wherein the semiconductor material region further comprises at least a lateral edge region of the cell array having a lowered dopant concentration at a surface region of the semiconductor material region compared to the dopant concentration of a first epitaxial layer on a semiconductor substrate, said surface region having a vertical depth from the surface of the semiconductor material region that embeds or encloses the source region and the body region, but does not exceed the depth of the trench so that the trench extends through the surface region and into, but not through a second epitaxial layer below the first epitaxial layer.

24. The semiconductor component of claim 23, wherein the lowered dopant concentration of the lateral edge region is below 10¹⁶ cm⁻

3.

25. The semiconductor component of claim 23, wherein the lateral edge region is at least as thick as a source and a channel region of the trench transistor semiconductor elements together.