Dual-sided chip attached modules

• US 7,863,734 B2
• Filed: 08/06/2008
• Issued: 01/04/2011
• Est. Priority Date: 05/16/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Sprogis, Edmund, Dalton, Timothy, Gambino, Jeffrey Peter, Muzzy, Christopher David, Sauter, Wolfgang, Jaffe, Mark David, Daubenspeck, Timothy Harrison, Bernstein, Kerry, Stamper, Anthony Kendall
• Primary Examiner(s): Parekh; Nitin
• Application Number:
  US12/186,655
• Publication Number:
  US 20090065925A1
• Time in Patent Office: 881 Days
• Field of Search: 257/723, 257/778, 257/774, 257/E23.169
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H05K 1/145 : Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/222 : Completing of printed circuits by adding non-printed jumper connections printed jumper connections H05K3/4685
• CPC Class Codes: Y10T 436/171538 : Urea or blood urea nitrogen
• CPC Class Codes: Y10T 436/172307 : Cyanide or isocyanide

Abstract

An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

Claims

1. An electronic device, comprising:

a first substrate having a first set of electrically conductive substrate pads on a first surface of said first substrate, a second set of electrically conductive substrate pads on a second and opposite surface of said first substrate, and a plurality of electrically conductive wires connecting substrate pads of said first set of substrate pads to corresponding substrate pads of said second set of substrate pads;

a second substrate having a third set of electrically conductive substrate pads on a first surface of said second substrate, a plurality of electrically conductive wires in said second substrate interconnecting combinations of substrate pads of said third set of substrate pads; and

an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on said first side and a second set of chip pads on said second side of said integrated circuit chip, chip pads of said first set of chip pads physically and electrically connected to corresponding substrate pads of said first set of substrate pads, and chip pads of said second set of chip pads physically and electrically connected to corresponding substrate pads of said third set of substrate pads.

2. The electronic device of claim 1, further including:

a first set of solder bumps physically and electrically connecting said chip pads of said first set of chip pads to said corresponding substrate pads of said first set of substrate pads; and

a second set of solder bumps physically and electrically connecting said chip pads of said second set of chip pads to said corresponding substrate pads of said third set of substrate pads.

3. The electronic device of claim 1, further including:

a set of solder bumps physically and electrically connecting said chip pads of said first set of chip pads to said corresponding pads of said first set of substrate pads; and

a set of wire bonds physically and electrically connecting said chip pads of said second set of chip pads to said corresponding substrate pads of said third set of substrate pads.

4. The electronic device of claim 1, further including:

a heatsink physically attached to a second surface of said second substrate, said second surface of said substrate opposite from said first surface of said second substrate.

5. The electronic device of claim 1, wherein said first surface and said second surface of said first substrate are opposite each other.

6. The electronic device of claim 1, wherein said first surface and said second surface of said first substrate share a common edge and are essentially perpendicular to each other.

7. The electronic device of claim 1, wherein said first substrate is a single or multilevel ceramic substrate, a single or multilevel organic substrate, a fiberglass substrate, a printed circuit board or a tape automated bonding substrate, and wherein said second substrate is a single or multilevel ceramic substrate, a single or multilevel organic substrate, a fiberglass substrate, a printed circuit board or a tape automated bonding substrate.

8. The electronic device of claim 1, further including:

an additional integrated circuit chip having a first side and an opposite second side, an additional first set of chip pads on said first side and an additional second set of chip pads on said second side of said additional integrated circuit chip, chip pads of said additional first set of chip pads physically and electrically connected to corresponding substrate pads of said first set of substrate pads, and chip pads of said additional second set of chip pads physically and electrically connected to corresponding substrate pads of said third set of substrate pads.

9. The electronic device of claim 8, wherein, one or more of said wires of said second substrate electrically connect selected chip pads of said second set of chips pads of said integrated circuit chip to selected chip pads of said additional second set of chips pads of said additional integrated circuit chip.

10. The electronic device of claim 1, said integrated circuit chip comprising:

one or more devices in a silicon-on-insulator substrate, said silicon-on-insulator substrate comprising a silicon layer on a top surface of an oxide layer and a pre-metal dielectric layer on a top surface of said silicon layer;

one or more first wiring levels on a top surface of said pre-metal dielectric layer, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer;

electrically conductive first contacts to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said first wiring levels in physical and electrical contact with said first contacts;

electrically conductive second contacts to said devices, one or more of said second contacts extending from said bottom surface of said oxide layer to said devices; and

one or more second wiring levels over a bottom surface of said oxide layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts.

11. The electronic device of claim 1, said integrated circuit chip comprising:

one or more first devices of a first silicon-on-insulator substrate, said first silicon-on-insulator substrate comprising a first oxide layer, a first silicon layer on said first oxide layer and a first lowermost dielectric layer on said first silicon layer;

one or more second devices of a second silicon-on-insulator substrate, said second silicon-on-insulator substrate comprising a second oxide layer, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;

a top surface of said first oxide layer bonded to a top surface of said second oxide layer;

electrically conductive first contacts to said second devices, said first contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer to said first devices;

electrically conductive second contacts to said first devices, said second contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said first and second oxide layers to those portions of said second devices formed in said second silicon layer; and

one or more second wiring levels over said second lowermost dielectric layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said first and second contacts.

12. The electronic device of claim 11, further including:

a heatsink physically attached to a second surface of said first substrate, said second surface of said substrate opposite from said first surface of said first substrate.

15. The electronic device of claim 12, further including:

an additional heatsink physically attached to a second surface of said second substrate, said second surface of said substrate opposite from said first surface of said second substrate.

13. An electronic device, comprising:

a first substrate having a first set of electrically conductive substrate pads and a second set of electrically conductive substrate pads on a first surface of said first substrate, and a plurality of electrically conductive wires connecting substrate pads of said first set of substrate pads to corresponding substrate pads of said second set of substrate pads;

a second substrate having a third set of electrically conductive substrate pads and a plurality of electrically conductive fourth substrate pads on a first surface of said second substrate, and a plurality of electrically conductive wires connecting substrate pads of said third set of substrate pads to corresponding substrate pads of said fourth set of substrate pads; and

an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on said first side and a second set of chip pads on said second side of said integrated circuit chip, chip pads of said first set of chip pads physically and electrically connected to corresponding substrate pads of said first set of substrate pads, and chip pads of said second set of chip pads physically and electrically connected to corresponding substrate pads of said third set of substrate pads.

14. The electronic device of claim 13, further including:

a first set of solder bumps physically and electrically connecting said chip pads of said first set of chip pads to said corresponding substrate pads of said first set of substrate pads; and

a second set of solder bumps physically and electrically connecting said chip pads of said second set of chip pads to said corresponding substrate pads of said third set of substrate pads.

16. The electronic device of claim 13, wherein said first and second substrates are flexible circuit carriers.

17. The electronic device of claim 13, further including:

an additional integrated circuit chip having a first side and an opposite second side, an additional first set of chip pads on said first side and an additional second set of chip pads on said second side of said additional integrated circuit chip, chip pads of said additional first set of chip pads physically and electrically connected to corresponding substrate pads of said first set of substrate pads, and chip pads of said additional second set of chip pads physically and electrically connected to corresponding substrate pads of said third set of substrate pads.

18. The electronic device of claim 17, wherein, one or more of said wires of said first substrate electrically connect selected chip pads of said first set of chips pads of said integrated circuit chip to selected chip pads of said additional first set of chips pads of said additional integrated circuit chip.

19. The electronic device of claim 18, wherein, one or more of said wires of said second substrate electrically connect selected chip pads of said second set of chips pads of said integrated circuit chip to selected chip pads of said additional second set of chips pads of said additional integrated circuit chip.

20. The electronic device of claim 13, said integrated circuit chip comprising:

one or more devices in a silicon-on-insulator substrate, said silicon-on-insulator substrate comprising a silicon layer on a top surface of an oxide layer and a pre-metal dielectric layer on a top surface of said silicon layer;

one or more first wiring levels on a top surface of said pre-metal dielectric layer, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer;

electrically conductive first contacts to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said first wiring levels in physical and electrical contact with said first contacts;

electrically conductive second contacts to said devices, one or more of said second contacts extending from said bottom surface of said oxide layer to said devices; and

one or more second wiring levels over a bottom surface of said oxide layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts.

21. The electronic device of claim 13, said integrated circuit chip comprising:

one or more first devices of a first silicon-on-insulator substrate, said first silicon-on-insulator substrate comprising a first oxide layer, a first silicon layer on said first oxide layer and a first lowermost dielectric layer on said first silicon layer;

one or more second devices of a second silicon-on-insulator substrate, said second silicon-on-insulator substrate comprising a second oxide layer, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;

a top surface of said first oxide layer bonded to a top surface of said second oxide layer;

electrically conductive first contacts to said second devices, said first contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer to said first devices;

electrically conductive second contacts to said first devices, said second contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said first and second oxide layers to those portions of said second devices formed in said second silicon layer; and

one or more second wiring levels over said second lowermost dielectric layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said first and second contacts.