Low fabrication cost, fine pitch and high reliability solder bump

• US 7,863,739 B2
• Filed: 10/31/2007
• Issued: 01/04/2011
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Soward; Ida M
• Application Number:
  US11/930,998
• Publication Number:
  US 20080048320A1
• Time in Patent Office: 1,161 Days
• Field of Search: 257737-738, 257/758, 257/E23.02, 257/E23.021
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Claims

1. A chip comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a metal pad over said dielectric layer;

a topmost insulating layer of said chip over said dielectric layer, wherein an opening in said topmost insulating layer of said chip exposes said metal pad, and wherein said topmost insulating layer of said chip is a polymer layer; and

a metal bump on said metal pad and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises a metal layer on said metal pad, in said opening and on said first top surface, and a copper pillar on said metal layer, over said opening and over said first top surface, wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar, and wherein said copper pillar has a second top surface higher than said first top surface.

2. The chip of claim 1, wherein said metal pad comprises aluminum.

3. The chip of claim 1, wherein said metal pad comprises copper.

4. The chip of claim 1, wherein said metal layer comprises titanium.

5. The chip of claim 1, wherein said metal layer comprises tantalum.

6. The chip of claim 1, wherein said metal layer has a thickness between 500 and 2,000 angstroms.

7. The chip of claim 1, wherein said metal bump further comprises an electroplated metal over said copper pillar, over said opening and over said first top surface.

8. The chip of claim 1, wherein said metal bump further comprises a nickel-containing layer on said copper pillar, over said opening and over said first top surface.

9. The chip of claim 1, wherein said metal bump further comprises a solder over said copper pillar, over said opening and over said first top surface.

10. The chip of claim 9, wherein said solder has a thickness between 30 and 100 micrometers.

11. The chip of claim 1, wherein said topmost insulating layer of said chip is a polyimide layer.

12. The chip of claim 1 further comprising multiple layers of interconnecting lines, multiple additional insulating layers and multiple metal vias in said multiple additional insulating layers and between said multiple layers of interconnecting lines, wherein said multiple additional insulating layers comprise an oxide, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines, and wherein said metal pad provides an electrical interface with said multiple layers of interconnecting lines.

13. A chip comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a metal pad over said dielectric layer;

a topmost insulating layer of said chip over said dielectric layer, wherein an opening in said topmost insulating layer of said chip exposes said metal pad, and wherein said topmost insulating layer of said chip is a polymer layer; and

a metal bump on said metal pad and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises a metal layer on said metal pad, in said opening and on said first top surface, a copper pillar on said metal layer, over said opening and over said first top surface, and a solder over said copper pillar, over said opening and over said first top surface, wherein said solder is connected to said copper pillar, wherein said copper pillar has a height between 10 and 100 micrometers, and wherein said copper pillar has a second top surface higher than said first top surface and a sidewall with a portion not covered by said solder.

14. The chip of claim 13, wherein said metal pad comprises aluminum.

15. The chip of claim 13, wherein said metal pad comprises copper.

16. The chip of claim 13, wherein said metal layer comprises titanium.

17. The chip of claim 13, wherein said metal layer comprises tantalum.

18. The chip of claim 13, wherein said metal layer has a thickness between 500 and 2,000 angstroms.

19. The chip of claim 13, wherein said metal bump further comprises a nickel layer between said copper pillar and said solder.

20. The chip of claim 13, wherein said topmost insulating layer of said chip is a polyimide layer.

21. The chip of claim 13 further comprising multiple layers of interconnecting lines, multiple additional insulating layers and multiple metal vias in said multiple additional insulating layers and between said multiple layers of interconnecting lines, wherein said multiple additional insulating layers comprise an oxide, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines, and wherein said metal pad provides an electrical interface with said multiple layers of interconnecting lines.

22. The chip of claim 13, wherein said solder has a thickness between 30 and 100 micrometers.

23. A chip comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a metal layer over said dielectric layer, wherein said metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad;

a topmost insulating layer of said chip over said dielectric layer, over said metal pad, over said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said topmost insulating layer of said chip is over a contact point of said metal pad, and said contact point is at a bottom of said opening, and wherein said topmost insulating layer of said chip is a polymer layer; and

a metal bump on said contact point and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises a titanium-containing layer on said contact point, in said opening and on said first top surface, and a copper pillar over said titanium-containing layer, over said opening and over said first top surface, wherein said copper pillar has a height between 10 and 100 micrometers, and wherein said copper pillar has a second top surface higher than said first top surface and a sidewall with a portion not covered by any solder, wherein said first top surface has a first region vertically under said metal bump and vertically over said metal pad and a second region vertically over the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region.

24. The chip of claim 23, wherein said metal pad comprises copper.

25. The chip of claim 23, wherein said titanium-containing layer comprises titanium nitride.

26. The chip of claim 23, wherein said metal bump further comprises a nickel-containing layer on said copper pillar, over said opening and over said first top surface.

27. The chip of claim 23, wherein said metal bump further comprises a solder over said copper pillar, over said opening and over said first top surface, wherein said solder is connected to said copper pillar.

28. The chip of claim 27, wherein said solder has a thickness between 30 and 100 micrometers.

29. The chip of claim 23, wherein said topmost insulating layer of said chip is a polyimide layer.

30. The chip of claim 23 further comprising multiple layers of interconnecting lines, multiple additional insulating layers and multiple metal vias in said multiple additional insulating layers and between said multiple layers of interconnecting lines, wherein said multiple additional insulating layers comprise an oxide, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines, and wherein said metal pad provides an electrical interface with said multiple layers of interconnecting lines.

31. A chip comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a metal layer over said dielectric layer, wherein said metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad;

a topmost insulating layer of said chip over said dielectric layer, over said metal pad, over said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said topmost insulating layer of said chip is over a contact point of said metal pad, and said contact point is at a bottom of said opening, and wherein said topmost insulating layer of said chip is a polymer layer; and

a metal bump on said contact point and on a first top surface of said topmost insulating layer of said chip, wherein said metal bump comprises an adhesion-barrier layer on said contact point, in said opening and on said first top surface, and a copper pillar over said adhesion-barrier layer, over said opening and over said first top surface, wherein said copper pillar has a height between 10 and 100 micrometers, and wherein said copper pillar has a second top surface higher than said first top surface, wherein said first top surface has a first region vertically under said metal bump and vertically over said metal pad and a second region vertically over the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region.

32. The chip of claim 31, wherein said metal pad comprises copper.

33. The chip of claim 31, wherein said metal bump further comprises a nickel-containing layer on said copper pillar, over said opening and over said first top surface.

34. The chip of claim 31, wherein said metal bump further comprises a solder over said copper pillar, over said opening and over said first top surface, wherein said solder is connected to said copper pillar.

35. The chip of claim 31, wherein said topmost insulating layer of said chip is a polyimide layer.

36. The chip of claim 31 further comprising multiple layers of interconnecting lines, multiple additional insulating layers and multiple metal vias in said multiple additional insulating layers and between said multiple layers of interconnecting lines, wherein said multiple additional insulating layers comprise an oxide, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines, and wherein said metal pad provides an electrical interface with said multiple layers of interconnecting lines.

37. The chip of claim 34, wherein said solder has a thickness between 30 and 100 micrometers.

38. A chip comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a first contact pad over said dielectric layer;

a second contact pad over said dielectric layer;

a polymer layer over said dielectric layer and said first and second contact pads and between said first and second contact pads, wherein a first opening in said polymer layer is over a first contact point of said first contact pad, and wherein a second opening in said polymer layer is over a second contact point of said second contact pad;

a first metal bump on said first contact point and on a top surface of said polymer layer, wherein said first metal bump is connected to said first contact point through said first opening; and

a second metal bump on said second contact point and on said top surface, wherein said second metal bump is connected to said second contact point through said second opening, wherein each of said first and second metal bumps comprises a metal layer on said first or second contact point, on a sidewall of said first or second opening and on said top surface, and a copper pillar on said metal layer, over said first or second opening and over said top surface, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar has a sidewall exposed, wherein said top surface between said first and second metal bumps is substantially coplanar.

39. The chip of claim 38, wherein said first contact pad comprises copper.

40. The chip of claim 38, wherein said metal layer comprises titanium.

41. The chip of claim 38, wherein said each of said first and second metal bumps further comprises a nickel-containing layer on said copper pillar, over said first or second opening and over said top surface.

42. The chip of claim 38, wherein said each of said first and second metal bumps further comprises a solder over said copper pillar, over said first or second opening and over said top surface, wherein said solder is connected to said copper pillar.

43. The chip of claim 42, wherein said solder has a thickness between 30 and 100 micrometers.

44. A chip comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a metallization structure over said dielectric layer, wherein said metallization structure comprises a copper layer;

a polymer layer over said dielectric layer and said metallization structure, wherein a first opening in said polymer layer is over a first contact point of said metallization structure, and wherein a second opening in said polymer layer is over a second contact point of said metallization structure, wherein said polymer layer is between said first and second contact points;

a first metal bump on said first contact point and a top surface of said polymer layer, wherein said first metal bump is connected to said first contact point through said first opening; and

a second metal bump on said second contact point and said top surface, wherein said second metal bump is connected to said second contact point through said second opening, wherein each of said first and second metal bumps comprises a metal layer on said first or second contact point, a sidewall of said first or second opening and said top surface, and a copper pillar on said metal layer and over said first or second opening and said top surface, wherein said copper pillar has a height between 10 and 100 micrometers, wherein said copper pillar has a sidewall exposed, wherein said top surface between said first and second metal bumps is substantially coplanar.

45. The chip of claim 44, wherein said metal layer comprises titanium.

46. The chip of claim 44, wherein said each of said first and second metal bumps further comprises a nickel-containing layer on said copper pillar and over said first or second opening and said top surface.

47. The chip of claim 44, wherein said each of said first and second metal bumps further comprises a solder over said copper pillar, said first or second opening and said top surface, wherein said solder is connected to said copper pillar.

48. The chip of claim 47, wherein said solder has a thickness between 30 and 100 micrometers.