Authenticating a device at a battery pack using a random number generator

• US 7,863,858 B2
• Filed: 06/10/2009
• Issued: 01/04/2011
• Est. Priority Date: 03/10/2006
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated), Sony Corporation (Sony Group Corp.)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated), Sony Corporation (Sony Group Corp.)
• Inventors: Gangstoe, Gunnar, Sato, Hideyuki, Aas, Arne
• Primary Examiner(s): TSO, EDWARD H
• Application Number:
  US12/482,375
• Publication Number:
  US 20090243539A1
• Time in Patent Office: 573 Days
• Field of Search: 320/106, 320/107, 320/110, 320/112, 710/52, 713/161, 713/184, 380/44
• US Class Current: 320/106
• CPC Class Codes: H02J 7/00045 Authentication, i.e. circuits for checking compatibility between one component, e.g. a battery or a battery charger, and another component, e.g. a power source
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator
• CPC Class Codes: H04L 9/3273 for mutual authentication network architectures or network communication protocols for achieving mutual authentication in a packet data network H04L63/0869

Abstract

Apparatus, method and computer program product are provided for battery management. In one implementation, a method of communication provided. The method includes enabling determining when a battery pack is coupled to a device, the battery pack including a battery management system. The method also includes generating a random number at the battery management system, the battery management system including battery monitoring circuitry, a processor, memory and a random number generator. The method includes using the random number to provide authentication and if authentication succeeds, enabling communication between the battery pack and the device.

Claims

1. A battery pack, comprising:

one or more battery cells;

a battery management system that authenticates a device at the battery management system and includes an integrated processor; and

a communication engine including a random number generator.

2. The battery pack of claim 1 further comprising:

a high-side NFET charge transistor coupled to a high-side NFET discharge transistor in series.

3. The battery pack of claim 2, where the battery management system is coupled to the high-side NFET charge transistor and the high-side NFET discharge transistor.

4. The battery pack of claim 1, where the integrated processor is configured to encrypt a random number generated by the random number generator using a first encryption key.

5. The battery pack of claim 4, where the integrated processor is configured to decrypt an encrypted random number received from the device using a second encryption key.

6. An apparatus, comprising:

a high-side NFET charge or discharge transistor operable to enable charging of one or more cells of a battery pack;

a battery management system that authenticates a device at the battery management system, where the battery management system is coupled to the high-side NFET charge or discharge transistor, and the battery management system includes a communication engine; and

a random number generator.

7. A device, comprising:

a first integrated processor;

a battery pack including;

one or more battery cells,

a battery management system that authenticates the device at the battery management system, and

a communication engine including a random number generator.

8. The device of claim 7, where the battery management system includes a second integrated processor that encrypts a random number generated by the random number generator using a first encryption key.

9. The device of claim 8, where the first integrated processor is configured to decrypt an encrypted random number using a second encryption key.

10. The device of claim 7, where the battery pack further includes a high-side NFET charge transistor coupled to a high-side NFET discharge transistor in series.

11. The device of claim 10, where the battery management system is coupled to the high-side NFET charge transistor and the high-side NFET discharge transistor.