Disposable built-in self-test devices, systems and methods for testing three dimensional integrated circuits
First Claim
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1. A method for self-testing an integrated circuit layer for a three-dimensional integrated circuit, comprising:
- integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested, the first circuit for forming a layer in a three-dimensional integrated circuit structure;
testing the first circuit using circuitry of the self-test circuit by employing the self-test circuit to simulate conditions of an assembled three-dimensional integrated circuit chip for which the first chip is a component; and
removing the self-test circuit by detaching the self-test circuit from the first circuit.
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Abstract
A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit.
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Citations
22 Claims
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1. A method for self-testing an integrated circuit layer for a three-dimensional integrated circuit, comprising:
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integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested, the first circuit for forming a layer in a three-dimensional integrated circuit structure; testing the first circuit using circuitry of the self-test circuit by employing the self-test circuit to simulate conditions of an assembled three-dimensional integrated circuit chip for which the first chip is a component; and removing the self-test circuit by detaching the self-test circuit from the first circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for self-testing an integrated circuit layer for a three-dimensional integrated circuit, comprising:
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integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested, the first circuit for forming a layer in a three-dimensional integrated circuit structure; joining the first circuit having the self-test circuit to at least one other layer to form the three-dimensional integrated circuit structure wherein the at least one other layer and the first circuit each include a self-test circuit; testing the three-dimensional integrated circuit structure using circuitry of the self-test circuit; and removing the self-test circuits by detaching the self-test circuits from the first circuit and the at least one other layer by dicing all layers to remove the self-test circuits. - View Dependent Claims (9, 10, 11, 12)
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13. An integrated circuit, comprising:
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a first chip portion configured to be integrated in a three-dimensional integrated circuit structure; and a self-test portion integrated on a same substrate with the first chip portion, the self-test portion including circuitry configured to test the first chip portion and the self-test portion being configured to be detachable from the first chip portion to permit disposal of the self-test portion after testing the first chip portion wherein the circuitry of the self-test portion includes built-in self-test circuits to simulate conditions of an assembled three-dimensional integrated circuit structure for which the first chip portion is a component. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A three-dimensional integrated circuit, comprising:
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a first chip portion; at least one other layer bonded to the first chip portion to form a three-dimensional integrated chip, the at least one other layer including functional devices which interact with circuitry formed on the first chip portion; and a self-test portion integrated on a same chip substrate with the first chip portion after removal from a wafer, the self-test portion including circuitry configured to test at least the first chip portion and the self-test portion being configured to be detachable from the first chip portion by severing the chip substrate to permit disposal of the self-test portion after testing at least the first chip portion. - View Dependent Claims (20, 21, 22)
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Specification