Driving circuit with impedence calibration and pre-emphasis functionalities

• US 7,863,936 B1
• Filed: 05/24/2010
• Issued: 01/04/2011
• Est. Priority Date: 12/01/2009
• Status: Expired due to Fees

• Current Assignee: Himax Imaging, Inc. (Himax Technologies Incorporated)
• Original Assignee: Himax Imaging, Inc. (Himax Technologies Incorporated)
• Inventors: Liu, Chih-Min, Yin, Ping-Hung, Huang, Kuo-Chan
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US12/785,505
• Time in Patent Office: 225 Days
• Field of Search: None
• US Class Current: 326/86
• CPC Class Codes: H03K 19/018564 with at least one differential stage H03K19/018578 takes precedence
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A driving circuit includes at least a driving unit, a first processing unit and a second processing unit. The driving circuit includes a first bias component, a second bias component, a first pre-emphasis unit, a second pre-emphasis unit, and a transmitter unit. The first bias component has a first node coupled to a first reference voltage and a second node for outputting a first bias current. The second bias component has a first node for draining a second bias current and a second node coupled to a second reference voltage different from the first reference voltage.

Claims

1. A driving circuit, comprising:

at least a driving unit, comprising;

a first bias component, having a first node coupled to a first reference voltage, and a second node for outputting a first bias current;

a second bias component, having a first node for draining a second bias current, and a second node coupled to a second reference voltage different from the first reference voltage;

a first pre-emphasis unit, for receiving a first driving signal and a first pre-emphasis control signal, and generating a first pre-emphasis output signal according to the first driving signal and the first pre-emphasis control signal;

a second pre-emphasis unit, for receiving a second driving signal and a second pre-emphasis control signal, and generating a second pre-emphasis signal according to the second driving signal and the second pre-emphasis control signal; and

a transmitter unit, coupled to a first output port a second port of the driving circuit, for receiving the first pre-emphasis signal and the second pre-emphasis signal;

a first processing unit, coupled to the first pre-emphasis unit for receiving a first input signal and generating the first driving signal and the first pre-emphasis control signal according to the first input signal; and

a second processing unit, coupled to the second pre-emphasis unit for receiving a second input signal and generating the second driving signal and the second pre-emphasis control signal according to the second input signal.

2. The driving circuit of claim 1, wherein the transmitter unit comprises:

a first transistor, having a control node coupled to the first pre-emphasis unit for receiving the first pre-emphasis signal, a first connection node coupled to the second node of the first bias component, and a second connection node coupled to the first output port of the driving circuit;

a second transistor, having a control node coupled to the second pre-emphasis unit for receiving the second pre-emphasis signal, a first connection node coupled to the second node of the first bias component, and a second connection node coupled to the second output port of the driving circuit;

a third transistor, having a control node coupled to the second pre-emphasis unit for receiving the second pre-emphasis signal, a first connection node coupled to the first output port of the driving circuit, and a second connection node coupled to the first node of the second bias component; and

a fourth transistor, having a control node coupled to the first pre-emphasis unit for receiving the first pre-emphasis signal, a first connection node coupled to the second output port of the driving circuit, and a second connection node coupled to the first node of the second bias component.

3. The driving circuit of claim 1, wherein at least one of the first processing unit and the second processing unit comprises:

a first delay cell, coupled to a corresponding pre-emphasis unit, for receiving a corresponding input signal and delaying the corresponding input signal to generate a corresponding driving signal;

a second delay cell, for receiving the corresponding input signal and delaying the corresponding input signal to generate a delayed signal; and

a ratio generator, coupled to the second delay cell and the first pre-emphasis unit, for receiving the corresponding input signal and the delayed signal and generating a corresponding pre-emphasis control signal according to the corresponding input signal and the delayed signal.

4. The driving circuit of claim 3, wherein the ratio generator is an XNOR logic gate.

5. The driving circuit of claim 3, wherein the ratio generator further receives a pre-emphasis enable signal for controlling whether the corresponding pre-emphasis control signal is set to be constant.

6. The driving circuit of claim 5, wherein the ratio generator comprises:

a plurality of NOR logic gates, comprising;

a first NOR logic gate, for receiving a pre-emphasis power down signal and the corresponding input signal to generate a first NOR signal, wherein the pre-emphasis power down signal is derived from the pre-emphasis enable signal; and

a second NOR logic gate, for receiving the pre-emphasis power down signal and the delayed signal to generate a second NOR signal;

a first transistor, having a control node for receiving the delayed signal, a first node coupled to the first reference voltage, and a second node;

a second transistor, having a control node for receiving the corresponding input signal, a first node coupled to the second node of the first transistor, and a second node coupled to an output port utilized for outputting the corresponding pre-emphasis control signal;

a third transistor, having a control node for receiving the first NOR signal, a first node coupled to the first reference voltage, and a second node;

a fourth transistor, having a control node for receiving the second NOR signal, a first node coupled to the second node of the third transistor, and a second node coupled to the output port;

a fifth transistor, having a control node for receiving the corresponding input signal, a first node coupled to the output port, and a second node;

a sixth transistor, having a control node for receiving the second NOR signal, a first node coupled to the second node of the fifth transistor, and a second node coupled to the second reference voltage;

a seventh transistor, having a control node for receiving the first NOR signal, a first node coupled to the output port, and a second node; and

an eighth transistor, having a control node for receiving the delayed signal, a first node coupled to the second node of the seventh transistor, and a second node coupled to the second reference voltage.

7. The driving circuit of claim 6, wherein at least one of the first ratio generator and the second ratio generator further comprises:

an inverter, coupled to the first NOR logic gate and the second NOR logic gate, for receiving the pre-emphasis enable signal to generate the pre-emphasis power down signal.

8. The driving circuit of claim 1, wherein at least one of the first pre-emphasis unit and the second pre-emphasis unit comprises:

a NOR logic gate, for receiving a corresponding driving signal and a power-down signal to generate a corresponding pre-emphasis output signal, wherein the power-down signal is derived from a corresponding pre-emphasis control signal.

9. The driving circuit of claim 8, wherein at least one of the first pre-emphasis unit and the second pre-emphasis unit further receives a power down signal for controlling the corresponding pre-emphasis signal being set constant.

10. The driving circuit of claim 9, wherein at least one of the first pre-emphasis unit and the second pre-emphasis unit further comprises:

an AND logic gate, for receiving the corresponding pre-emphasis control signal and a logic control signal to generate the power-down signal, wherein the logic control signal is derived from the power down signal.

11. The driving circuit of claim 10, wherein at least one of the first pre-emphasis unit and the second pre-emphasis unit further comprises:

an inverter, for receiving the power down signal to generate the logic control signal.

12. The driving circuit of claim 2, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are of a same conductive type.

13. The driving circuit of claim 2, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor is an N-channel MOS (NMOS) transistor.

14. The driving circuit of claim 2, wherein the first input signal and the second input signal are a differential signal pair.

15. The driving circuit of claim 1, wherein each of the first bias component and the second bias component is a resistor.

16. The driving circuit of claim 1, wherein the driving circuit comprises a plurality of driving units each coupled between the first reference voltage and the second reference voltage;

and the driving circuit further comprises;

a calibration unit, coupled to the driving units, for activating at least one of the driving units according to an output signal of one of the first output port and the second port of the driving circuit.

17. The driving circuit of claim 16, wherein the calibration unit comprises:

a target voltage generator, for generating a target voltage;

a comparator, coupled to the target voltage generator and one of the first output port and the second port of the driving circuit, for comparing a voltage level of the output signal with the target voltage to generate a comparison output; and

a control logic, coupled to the comparator, for generating a control signal to control a number of activated driving units according to the comparison output.

18. The driving circuit of claim 17, wherein the target voltage is set according to at least an impedance of each load driven by the driving circuit and impedances of the first bias component and the second bias component.

19. The driving circuit of claim 17, wherein the control logic comprises:

a clock generator, for generating at least a first clock signal according to a reference clock, wherein when the voltage level of the output signal is substantially equal to the target voltage, the comparison output generated from the comparator stops the clock generator from generating the first clock signal; and

a counter, coupled to the clock generating, for generating a counter value according to the first clock signal, wherein the control signal is derived from the counter value.

20. The driving circuit of claim 17, wherein the control logic comprises:

a control signal generator, coupled to the counter, for converting the counter value into the control signal.

21. The driving circuit of claim 17, wherein the clock generator further generates a second clock signal according to the reference clock, where the first clock signal and the second clock signal are 180 degrees out of phase;

and the comparator comprises;

a sampling and adjusting element, for sampling the target voltage to generate a sampled voltage at an output node according to the first clock signal, and for adjusting the sampled voltage according to a difference between the target voltage and the voltage level of the output signal to thereby generate an adjusted voltage; and

a determining element, coupled to the sampling and adjusting element, for generating the comparison output according to a voltage level at the output node of the sampling and adjusting element.

22. The driving circuit of claim 1, wherein the first reference voltage and the second voltage reference comply with a Mobile Processor Interface (MIPI) standard.