Logic based on the evolution of nonlinear dynamical systems

• US 7,863,937 B2
• Filed: 02/27/2009
• Issued: 01/04/2011
• Est. Priority Date: 10/07/2003
• Status: Expired due to Term

• Current Assignee: CDI2, LLC, University of Florida Research Foundation, Incorporated (State University System of Florida)
• Original Assignee: Control Dynamics, Inc., University of Florida Research Foundation, Incorporated (State University System of Florida)
• Inventors: Sinha, Sudeshna, Miliotis, Abraham, Ditto, William L., Murali, Krishnamurthy
• Primary Examiner(s): Cho; James H.
• Assistant Examiner(s): Crawford; Jason
• Application Number:
  US12/394,991
• Publication Number:
  US 20100219858A1
• Time in Patent Office: 676 Days
• Field of Search: 326 37- 41, 326 46- 47, 326/104
• US Class Current: 326/104
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.

Claims

1. A logic gate for implementing logical expressions, the logic gate comprising:

at least one logic gate input for receiving at least one input logic gate signal and at least one control signal;

at least one output for producing a logic gate output signal;

a nonlinear updater that operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal, the nonlinear updater electrically coupled to the logic gate input and comprises a nonlinear updater output to provide a nonlinear updater output signal, and configured to apply a nonlinear function to the input logic gate signal in response to the control signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal; and

a comparator electrically coupled to the output of the logic gate and the output of the nonlinear updater, wherein the comparator comprises a comparator input adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear updater output signal to the reference threshold value.

2. The logic gate of claim 1, further comprising:

a feedback path coupling the nonlinear updater output to a nonlinear updater input, wherein the nonlinear updater is associated with a timing signal to iteratively apply the nonlinear function to the input logic gate signal.

3. The logic gate of claim 2, wherein the nonlinear output signal comprises a current state of the nonlinear updater as a result of iteratively applying the nonlinear function to the input logic gate signal.

4. The logic gate of claim 1, wherein the nonlinear updater output signal represents a different logical expression for each iterative application of the nonlinear function to the input logic gate signal.

5. The logic gate of claim 1, wherein the control signal comprises a global control parameter that is fixed for a given duration corresponding to time period in which the input logic gate signal evolves into the plurality of different logic gates.

6. The logic gate of claim 1, wherein the control signal comprises an initial state of the nonlinear updater.

7. The logic gate of claim 1, wherein the logical gate output corresponds to an AND logic gate.

8. The logic gate of claim 1, wherein the logical gate output corresponds to a NAND logic gate.

9. The logic gate of claim 1, wherein the logical gate output corresponds to an OR logic gate.

10. The logic gate of claim 1, wherein the logical gate output corresponds to a NOR logic gate.

11. The logic gate of claim 1, wherein the logical gate output corresponds to a XNOR logic gate.

12. The logic gate of claim 1, wherein the logical gate output corresponds to a XOR logic gate.

13. The logic gate of claim 1, wherein the logical gate output corresponds to a NOT logic gate.

14. The logic gate of claim 1, wherein the control signal comprises a global control parameter that is fixed for a first given duration corresponding to time period in which the input logic gate signal evolves into the plurality of different logic gates, and wherein after the first given duration the global control parameter is adjusted for a second given duration.

15. A method of changing functionality of a logic gate, the method comprising:

receiving at least one input logic gate signal and at least one control signal;

operating a nonlinear updater as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal;

applying a nonlinear function to the input logic gate signal in response to the control signal;

producing, in response to the applying, a nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal;

operating a comparator electrically coupled to an output of the logic gate and an output of the nonlinear updater, wherein the comparator comprises an input adapted to receive a reference threshold value;

comparing, in response to the operating, the nonlinear output signal to the reference threshold value; and

producing, in response to the comparing, a logical gate output signal.

16. The method of claim 15, further comprising:

coupling the output of the nonlinear updater an input of the nonlinear updater;

receiving, by the nonlinear updater, a timing signal; and

iteratively applying, by the nonlinear updater, the nonlinear function to the input logic gate signal.

17. The method of claim 15,

fixing a global parameter at the comparator for a given duration corresponding to time period in which the input logic gate signal evolves into the plurality of different logic gates.