Ternary and higher multi-value digital scramblers/descramblers
First Claim
1. A method of descrambling a sequence of p scrambled n-state symbols with n>
- 2 and p>
1 into a sequence of p descrambled n-state symbols, an n-state symbol being able to assume one of n states, comprising;
inputting a first scrambled n-state symbol of the sequence of p scrambled n-state symbols on a first input of a descrambling n-state function;
inputting a second n-state symbol on a second input of the descrambling n-state function;
generating by a processor of a descrambled n-state symbol in accordance with the descrambling n-state function, wherein a truth table representing the descrambling n-state function is implemented in a memory that is accessed by the processor;
wherein a relationship between the first scrambled n-state symbol which may be called A, the second n-state symbol which may be called B and the descrambled n-state symbol which may be called C is defined by the n-state truth table that is commutative and self reversing and that satisfies the following equations for all possible states of A and B;
A sc B=C;
(1)
C sc B=A; and
(2)
A sc C=B; and
(3)repeating the previous steps until all symbols of the sequence of p scrambled n-state symbols have been descrambled by the processor.
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Abstract
Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
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Citations
19 Claims
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1. A method of descrambling a sequence of p scrambled n-state symbols with n>
- 2 and p>
1 into a sequence of p descrambled n-state symbols, an n-state symbol being able to assume one of n states, comprising;inputting a first scrambled n-state symbol of the sequence of p scrambled n-state symbols on a first input of a descrambling n-state function; inputting a second n-state symbol on a second input of the descrambling n-state function; generating by a processor of a descrambled n-state symbol in accordance with the descrambling n-state function, wherein a truth table representing the descrambling n-state function is implemented in a memory that is accessed by the processor; wherein a relationship between the first scrambled n-state symbol which may be called A, the second n-state symbol which may be called B and the descrambled n-state symbol which may be called C is defined by the n-state truth table that is commutative and self reversing and that satisfies the following equations for all possible states of A and B;
A sc B=C;
(1)
C sc B=A; and
(2)
A sc C=B; and
(3)repeating the previous steps until all symbols of the sequence of p scrambled n-state symbols have been descrambled by the processor. - View Dependent Claims (2, 3, 4, 5, 6)
- 2 and p>
-
7. An apparatus for descrambling a plurality of scrambled n-state symbols including a first scrambled n-state symbol, each n-state symbol enabled to assume one of n states with n>
- 2, comprising;
a descrambling device having a first and a second input and an output, the first input enabled to receive a signal representing the first scrambled n-state symbol, the second input enabled to receive a signal representing a second n-state symbol and the output providing a signal representing a descrambled n-state symbol; wherein a relationship between the first scrambled n-state symbol which may be called A, the second n-state symbol which may be called B and the descrambled n-state symbol which may be called C is determined by a commutative self reversing n-state logic function sc, that satisfies the following equations for all possible states of A and B;
A sc B=C;
(1)
C sc B=A; and
(2)
A sc C=B; and
(3)wherein the descrambling device includes a memory that implements a truth table that defines the commutative self reversing n-state logic function sc. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
- 2, comprising;
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15. A method for scrambling a sequence of p n-state symbols with p>
- 1, including a first n-state symbol, each n-state symbol enabled to assume one of n states with n>
2, each n-state symbol being represented by a signal, comprising;inputting the first n-state symbol of the sequence of p n-state symbols on a first input of a scrambling n-state function; inputting a second n-state symbol on a second input of the scrambling n-state function; generating by a processor of a scrambled n-state symbol in accordance with the scrambling n-state function, wherein a truth table representing the scrambling n-state function is implemented in a memory that is accessed by the processor; wherein a relationship between the first n-state symbol which may be called A, the second n-state symbol which may be called B and the scrambled n-state symbol which may be called C is defined by the n-state truth table that is commutative and self reversing and that satisfies the following equations for all possible states of A and B;
A sc B=C;
(1)
C sc B=A; and
(2)
A sc C=B; and
(3)repeating the previous steps until all symbols of the sequence of p n-state symbols have been scrambled by the processor. - View Dependent Claims (16, 17, 18, 19)
- 1, including a first n-state symbol, each n-state symbol enabled to assume one of n states with n>
Specification