Tiled electronic display structure

• US 7,864,136 B2
• Filed: 08/30/2006
• Issued: 01/04/2011
• Est. Priority Date: 02/17/1998
• Status: Expired due to Fees

• Current Assignee: MEC Management, LLC (Three Affiliated Tribes of the Fort Berthold Reservation, North Dakota)
• Original Assignee: Transpacific Infinity LLC
• Inventors: Atherton, James Harold, Hechis, Dennis J., Shen, Zilan, Matthies, Dennis Lee, Stewart, Roger Green, Busta, Heinz H.
• Primary Examiner(s): Dharia; Prabodh M
• Application Number:
  US11/468,744
• Publication Number:
  US 20080174515A1
• Time in Patent Office: 1,588 Days
• Field of Search: 345/1.1, 345/1.3, 345/205, 345/206, 345/90, 345/204, 345/163, 348/184, 348/383, 349/151, 349/1, 349/22, 313/586, 313/483, 273/153.S
• US Class Current: 345/1.3
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G09G 2300/026 Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/048 using evaluation of the usage time
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H10K 50/85 Arrangements for extracting light from the devices
• CPC Class Codes: H10K 50/86 Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/18 Tiled displays
• CPC Class Codes: H10K 59/875 Arrangements for extracting light from the devices
• CPC Class Codes: H10K 59/8791 Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/8792 comprising light absorbing layers, e.g. black layers

Abstract

A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.

Claims

1. An apparatus, comprising:

a circuit board having a first side and a second side;

a display medium disposed on the first side of the circuit board, wherein the display medium has a plurality of pixels thereon, and wherein the plurality of pixels are arranged in one or more pixel areas;

a plurality of electrodes electrically coupled to the one or more pixel areas; and

an electronic circuit disposed on the second side of the circuit board;

wherein the circuit board includes a plurality of vias extending from the second side of the circuit board to the plurality of pixels;

wherein at least some of the plurality of vias are configured to electrically couple the electronic circuit with one or more of the plurality of electrodes; and

wherein at least one of the plurality of pixels is offset from a center of a pixel area to provide a space for at least one of the plurality of vias.

2. The apparatus of claim 1, wherein one or more of the plurality of pixels are located within a pixel area in a location configured to allow at least one of the plurality of vias to couple to one or more electrodes within the pixel area without interfering with a regular spacing of the plurality of pixels.

3. The apparatus of claim 1, further comprising a transparent layer disposed on the first side of the circuit board over at least a portion of the display medium.

4. The apparatus of claim 1, further comprising an optical interface coupled to the electronic circuit and configured to couple the electronic circuit to one or more optical devices.

5. The apparatus of claim 1, wherein one or more of the plurality of vias are disposed in a peripheral area of the circuit board.

6. The apparatus of claim 1, wherein a distance between a center of one or more edge pixels of the display and an edge of the circuit board is less than or equal to approximately one-half of the pixel pitch.

7. The apparatus of claim 1, wherein a distance between a center of one or more edge pixels of the display and an edge of the circuit board is less than one-half of the pixel pitch.

8. An apparatus, comprising:

a transparent plate;

a display medium disposed on the transparent plate, wherein the display medium has a plurality of pixels thereon, and wherein the plurality of pixels are arranged in one or more pixel areas;

a plurality of electrodes electrically coupled to the one or more pixel areas;

a circuit board, wherein the display medium is at least partially disposed between the transparent plate and the circuit board;

at least one of an insulating layer or a metal layer disposed between the display medium and the circuit board;

wherein the circuit board includes a plurality of vias extending through the circuit board to the plurality of pixels of the display medium and configured to electrically couple the electronic circuit with one or more of the plurality of electrodes.

9. The apparatus of claim 8, wherein one or more of the plurality of pixels are located within a pixel area in a location configured to allow the one or more vias to couple to the one or more electrodes within the pixel area without interfering with a regular spacing of the plurality of pixels.

10. The apparatus of claim 8, further comprising an optical interface coupled to the electronic circuit and configured to couple the electronic circuit to one or more optical devices.

11. The apparatus of claim 8, wherein one or more of the plurality of vias are disposed in a peripheral area of the circuit board.

12. The apparatus of claim 8, wherein a distance between a center of one or more edge pixels of the display and an edge of the circuit board is less than or equal to approximately one-half of the pixel pitch.

13. The apparatus of claim 8, wherein one or more of the plurality of pixels are offset from a center of a pixel area.

14. An apparatus, comprising:

a frame;

a plurality of displays disposed within the frame in a tile arrangement;

a plurality of flexible connectors disposed on the frame and configured to electrically couple with the plurality of displays to allow control of the plurality of displays as a combined display, wherein the plurality of flexible connectors are also configured to push the plurality of displays toward a front plate;

wherein at least one of the plurality of displays includes;

a circuit board having a first side and a second side;

a display medium disposed on the first side of the circuit board, wherein the display medium has a plurality of pixels thereon, and wherein the plurality of pixels are arranged in one or more pixel areas;

a plurality of electrodes configured to be in electrical communication with the one or more pixel areas; and

an electronic circuit disposed on the second side of the circuit board;

wherein the circuit board includes a plurality of vias extending from the second side of the circuit board to the plurality of pixels; and

wherein at least some of the plurality of vias are configured to electrically couple the electronic circuit with one or more of the plurality of electrodes.

15. The apparatus of claim 14, wherein one or more of the plurality of vias are disposed in a peripheral area of the circuit board.

16. The apparatus of claim 14, further comprising a transparent layer disposed on the first side of the circuit board over at least a portion of the display medium.

17. The apparatus of claim 14, where the circuit board comprises one or more of a ceramic, a glass ceramic, a glass, or combinations thereof.

18. The apparatus of claim 14, further comprising an optical interface coupled to the electronic circuit and configured to couple the electronic circuit to one or more optical devices.

19. The apparatus of claim 14, wherein one or more of the plurality of pixels are offset from a center of a pixel area.

20. The apparatus of claim 14, wherein one pixel area has approximately 25 percent occupied by all pixels within the pixel area.

21. The apparatus of claim 14, wherein one or more of the plurality of pixels are located within a pixel area in a location configured to allow at least one of the plurality of vias to couple to the one or more electrodes within the pixel area without interfering with a regular spacing of the plurality of pixels.

22. A tiled display structure, comprising:

a frame;

a panel mounted in the frame, wherein the panel has both a first surface and a second surface opposite the first surface;

a plurality of connectors arranged on the first surface of the panel, wherein the connectors are configured to provide at least one of power, data, or timing information;

a plurality of display tiles mounted on the first surface of the panel; and

a float-glass plate disposed over the plurality of display tiles;

wherein at least one of the plurality of display tiles includes a plurality of pixels; and

wherein at least one of the plurality of pixels comprises a distinct portion of display material physically separated from display material of any other pixel.

23. The tiled display structure of claim 22, wherein the plurality of connectors are solder-type connections.

24. The tiled display structure of claim 22, wherein the plurality of connectors are plug-type connectors.

25. The tiled display structure of claim 22, wherein the float-glass plate, the panel, and the frame form a hermetic seal.

26. A tiled display structure, comprising:

a frame having a peripheral area;

a plurality of spring elements arranged in the peripheral area; and

a plurality of connectors arranged inside the peripheral area, wherein the plurality of connectors are configured to provide at least one of power, timing, or data information; and

a plurality of display tiles mounted within the frame and over the plurality of connectors, wherein the plurality of display tiles are confined within the peripheral area of the frame by the plurality of spring elements;

wherein each display tile includes a plurality of pixels, and

wherein each pixel comprises a distinct portion of display material physically separated from the display material of any other pixel.

27. The tiled display structure of claim 26, wherein the plurality of connectors comprise at least one flexible connector.

28. The tiled display structure of claim 26, further comprising a float-glass plate disposed over the plurality of display tiles.

29. The tiled display structure of claim 26, wherein the spring elements align the tiles within the tiled display structure.

30. A display tile, comprising:

a first transparent sheet having both a first surface and a second surface opposite the first surface;

a plurality of dark stripes arranged in a matrix of rows and columns, wherein the plurality of dark stripes are disposed adjacent to the first surface; and

a plurality of pixels arranged in a matrix on the second surface;

wherein the plurality of dark stripes are configured to allow light emitted from the plurality of pixels to exit the display tile.

31. The display tile of claim 30, further comprising a second transparent sheet having a third surface, and a fourth surface opposite the third surface, wherein the fourth surface is disposed adjacent to the first surface.

32. The display tile of claim 31, wherein the dark stripes have substantially equal widths, and wherein a spacing between the dark stripes approximately equals the pixel pitch.

33. The display tile of claim 32, further comprising:

an antireflection coating disposed on the third surface; and

an ambient light absorber or a color filter disposed in, or on, the third surface.

34. The display tile of claim 32, further comprising a diffuser coating disposed on the third surface.

35. The display tile of claim 31, wherein a thickness of the first transparent sheet, and a width and a spacing of the dark stripes are configured such that substantially no light emitted from a pixel would be blocked as viewed from an angle normal to the display tile.

36. The display tile of claim 31, wherein widths of the dark dark stripes (W_m) satisfy the following criteria:

W_m≧

2d_c; and

W_m≦

P−

d_p−

2d_c;

where P is a pixel pitch, d_p is a pixel width, d_c=t_glass×

tan(Θ

_c), t_glass is a thickness of the first transparent sheet, and Θ

_c is a critical angle.

37. The display tile of claim 31, further comprising a plurality of mullions configured to join the display tile with other display tiles, wherein the plurality of mullions comprise a top surface having substantially a same color and substantially a same width as the plurality of dark stripes.

38. The display tile of claim 37, wherein the plurality of mullions comprise a bottom stem having light-colored or transparent sides.

39. A display structure, comprising a plurality of display tiles arranged in a matrix and separated by gaps, wherein the display tiles include:

a first transparent sheet having both a first surface and a second surface opposite the first surface;

a plurality of dark stripes arranged in a matrix of rows and columns, wherein the plurality of dark stripes are disposed adjacent to the first surface; and

a plurality of pixels arranged in a matrix on the second surface;

wherein the plurality of dark stripes are configured to allow light emitted from the plurality of pixels to exit the display structure.

40. The display structure of claim 39, wherein a thickness of the first transparent sheet, and a width and a spacing of the dark stripes are configured such that gaps between a particular display tile and its neighboring display tiles are substantially hidden as viewed from an angle normal to the particular display tile.

41. A cathodoluminescent display device, comprising:

a plurality of pixels, wherein at least one of the plurality of pixels includes a phosphor;

a cathode configured to emit an electron beam; and

a deflection unit comprising at least one electrostatic deflection grid and configured to raster the electron beam across the plurality of pixels.

42. The cathodoluminescent display device of claim 41, wherein the cathode is a thermionic cathode.

43. The cathodoluminescent display device of claim 41, wherein the cathode is a field-emissive cathode.

44. The cathodoluminescent display device of claim 41, wherein the deflection unit further comprises an electromagnetic deflection coil.

45. The cathodoluminescent display device of claim 44, further comprising at least one electrostatic focusing grid configured to focus the electron beam.

47. The cathodoluminescent display device of claim 41, further comprising at least one other cathode configured to emit another electron beam.

51. The cathodoluminescent display device of claim 47, wherein the deflection unit comprises a plurality of electromagnetic deflection coils.

46. A cathodoluminescent display device, comprising:

a plurality of pixels, wherein at least one of the plurality of pixels includes a phosphor;

a cathode configured to emit an electron beam; and

a deflection unit configured to raster the electron beam across the plurality of pixels;

wherein the cathode and the deflection unit are configured to emit and deflect a defocused electron beam that spreads across more than one of the plurality of pixels.

48. A cathodoluminescent display device, comprising:

a plurality of pixels, where at least one of the plurality of pixels includes a phosphor;

a first cathode configured to emit a first electron beam;

a second cathode configured to emit a second electron beam;

a deflection unit configured to raster the electron beam across the plurality of pixels; and

at least one electrostatic deflection grid associated with the first cathode and at least one electrostatic deflection grid associated with the second cathode.

49. The cathodoluminescent display device of claim 48, wherein the plurality of pixels are arranged in a two dimensional matrix of rows and columns, and wherein each deflection grid is configured to direct an electron beam across a row of pixels.

50. The cathodoluminescent display device of claim 49, further comprising a control grid associated with each cathode and configured to turn on and off the electron beam emitted by the associated cathode.

52. A cathodoluminescent display device, comprising:

a plurality of pixels, wherein at least one of the plurality of pixels includes a phosphor;

a first cathode configured to emit a first electron beam;

a second cathode configured to emit a second electron beam; and

a deflection unit configured to raster at least one of the first or second electron beams across the plurality of pixels;

wherein the deflection unit comprises a plurality of electromagnetic deflection coils; and

wherein the plurality of electromagnetic deflection coils are configured to generate a single magnetic field to deflect the first and second electron beams at the same time.

53. A cathodoluminescent display device, comprising:

a plurality of pixels, wherein at least one of the plurality of pixels includes a phosphor;

a first cathode configured to emit a first electron beam;

a second cathode configured to emit a second electron beam; and

a deflection unit configured to raster at least one of the first or second electron beams across the plurality of pixels;

wherein the deflection unit comprises a plurality of electromagnetic deflection coils; and

wherein the plurality of electromagnetic deflection coils are configured to raster the first and second electron beams provided by their associated cathodes individually.