Programming analog memory cells for reduced variance after retention

• US 7,864,573 B2
• Filed: 02/23/2009
• Issued: 01/04/2011
• Est. Priority Date: 02/24/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Perlmutter, Uri
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US12/390,522
• Publication Number:
  US 20090213654A1
• Time in Patent Office: 680 Days
• Field of Search: 365/185.03, 365/185.19, 365/185.24, 365/185.21, 365/185.22, 365/185.28
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method includes defining a nominal level of a physical quantity to be stored in analog memory cells for representing a given data value. The given data value is written to the cells in first and second groups of the cells, which have respective first and second programming responsiveness such that the second responsiveness is different from the first responsiveness, by applying to the cells in the first and second groups respective, different first and second patterns of programming pulses that are selected so as to cause the cells in the first and second groups to store respective levels of the physical quantity that fall respectively in first and second ranges, such that the first range is higher than and the second range is lower than the nominal level. The given data value is read from the cells at a later time.

Claims

1. A method for data storage in analog memory cells, the method comprising:

defining a nominal level of a physical quantity to be stored in the analog memory cells for representing a given data value;

writing, at a first time, the given data value to the analog memory cells in first and second groups of the analog memory cells, which have respective first and second programming responsiveness such that the second programming responsiveness is different from the first programming responsiveness, by applying to the analog memory cells in the first and second groups respective, different first and second patterns of programming pulses that are selected so as to cause the analog memory cells in the first and second groups to store respective levels of the physical quantity that fall respectively in first and second ranges of the levels, such that the first range is higher than the nominal level and the second range is lower than the nominal level; and

at a second time, subsequent to the first time, reading the given data value from the analog memory cells in the first and second groups.

2. The method according to claim 1, wherein the second programming responsiveness is lower than the first programming responsiveness.

3. The method according to claim 1, wherein the second programming responsiveness is higher than the first programming responsiveness.

4. The method according to claim 1, wherein the analog memory cells comprise Flash memory cells, and wherein the physical quantity comprises electrical charge.

5. The method according to claim 1, wherein the nominal level comprises one of multiple nominal levels of the physical quantity that represent respective multiple data values to be stored in the analog memory cells, and wherein reading the given data value comprises sensing the levels of the physical quantity stored in the analog memory cells in the first and second groups, and comparing the sensed levels to one or more read thresholds.

6. The method according to claim 1, wherein applying the first and second patterns comprises:

defining a verification threshold;

applying a given number of the programming pulses to the analog memory cells; and

after applying the given number, lowering the verification threshold and continuing to apply the programming pulses selectively to only the analog memory cells having the levels of the physical quantity that are lower than the verification threshold.

7. The method according to claim 1, wherein applying the first and second patterns comprises:

defining a verification threshold;

applying the programming pulses to the analog memory cells in both the first and the second groups until a predefined portion of the levels of the physical quantity in the analog memory cells exceeds the verification threshold; and

after the predefined portion exceeds the verification threshold, continuing to apply the programming pulses selectively to only the analog memory cells having the levels of the physical quantity that are lower than the verification threshold.

8. The method according to claim 7, wherein applying the programming pulses comprises determining that the predefined portion exceeds the verification threshold by comparing the levels in the analog memory cells to the verification threshold and counting the levels that exceed the verification threshold.

9. The method according to claim 7, wherein applying the programming pulses comprises estimating a number of the programming pulses that are expected to cause the predefined portion of the levels to exceed the verification threshold, and applying the estimated number of the programming pulses.

10. The method according to claim 7, wherein applying the programming pulses comprises lowering the verification threshold after the predefined portion exceeds the verification threshold.

11. The method according to claim 7, wherein continuing to apply the programming pulses comprises applying the programming pulses only until another predefined portion of the levels exceeds the verification threshold.

12. The method according to claim 11, wherein continuing to apply the programming pulses comprises determining that the other predefined portion exceeds the verification threshold by comparing the levels in the analog memory cells to the verification threshold and counting the levels that exceed the verification threshold.

13. The method according to claim 11, wherein continuing to apply the programming pulses comprises estimating a number of additional programming pulses that are expected to cause the other predefined portion of the levels to exceed the verification threshold, and applying the estimated number of the additional programming pulses.

14. A data storage apparatus, comprising:

a plurality of analog memory cells; and

Reading/Writing (R/W) circuitry, which is coupled to the analog memory cells and is configured to define a nominal level of a physical quantity to be stored in the analog memory cells for representing a given data value, to write, at a first time, the given data value to the analog memory cells in first and second groups of the analog memory cells, which have respective first and second programming responsiveness such that the second programming responsiveness is different from the first programming responsiveness, by applying to the analog memory cells in the first and second groups respective, different first and second patterns of programming pulses that are selected so as to cause the analog memory cells in the first and second groups to store respective levels of the physical quantity that fall respectively in first and second ranges of the levels, such that the first range is higher than the nominal level and the second range is lower than the nominal level, and, at a second time subsequent to the first time, to read the given data value from the analog memory cells in the first and second groups.

15. The apparatus according to claim 14, wherein the second programming responsiveness is lower than the first programming responsiveness.

16. The apparatus according to claim 14, wherein the second programming responsiveness is higher than the first programming responsiveness.

17. The apparatus according to claim 14, wherein the analog memory cells comprise Flash memory cells, and wherein the physical quantity comprises electrical charge.

18. The apparatus according to claim 14, wherein the nominal level comprises one of multiple nominal levels of the physical quantity that represent respective multiple data values to be stored in the analog memory cells, and wherein the R/W circuitry is configured to read the given data value by sensing the levels of the physical quantity stored in the analog memory cells in the first and second groups and comparing the sensed levels to one or more read thresholds.

19. The apparatus according to claim 14, wherein the R/W circuitry is configured to define a verification threshold, to apply a given number of the programming pulses to the analog memory cells, and, after applying the given number, to lower the verification threshold and to continue to apply the programming pulses selectively to only the analog memory cells having the levels of the physical quantity that are lower than the verification threshold.

20. The apparatus according to claim 14, wherein the R/W circuitry is configured to define a verification threshold, to apply the programming pulses to the analog memory cells in both the first and the second groups until a predefined portion of the levels of the physical quantity in the analog memory cells exceeds the verification threshold, and, after the predefined portion exceeds the verification threshold, to continue to apply the programming pulses selectively to only the analog memory cells having the levels of the physical quantity that are lower than the verification threshold.

21. The apparatus according to claim 20, wherein the R/W circuitry is configured to compare the levels in the analog memory cells to the verification threshold and to count the levels that exceed the verification threshold, so as to determine that the predefined portion exceeds the verification threshold.

22. The apparatus according to claim 20, wherein the R/W circuitry is configured to accept an estimate of a number of the programming pulses that are expected to cause the predefined portion of the levels to exceed the verification threshold, and to continue to apply the programming pulses selectively after applying the estimated number of the programming pulses to the memory cells.

23. The apparatus according to claim 20, wherein the R/W circuitry is configured to lower the verification threshold after the predefined portion exceeds the verification threshold.

24. The apparatus according to claim 20, wherein the R/W circuitry is configured to continue to apply the programming pulses selectively only until another predefined portion of the levels exceeds the verification threshold.

25. The apparatus according to claim 24, wherein the R/W circuitry is configured to compare the levels in the analog memory cells to the verification threshold and to count the levels that exceed the verification threshold, so as to determine that the other predefined portion exceeds the verification threshold.

26. The apparatus according to claim 24, wherein the R/W circuitry is configured to accept an estimate of a number of additional programming pulses that are expected to cause the other predefined portion of the levels to exceed the verification threshold, and to apply selectively the estimated number of the additional programming pulses.