Partially reconfigurable memory cell arrays

• US 7,864,620 B1
• Filed: 03/19/2009
• Issued: 01/04/2011
• Est. Priority Date: 03/19/2009
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pedersen, Bruce B.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/407,750
• Time in Patent Office: 656 Days
• Field of Search: 365/154, 365/156, 365/185.05, 365/185.23, 365/230.06, 365/230.08, 365/189.16
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Partial reconfiguration techniques and reconfiguration circuitry are provided that allow portions of a memory cell array to be reconfigured with new reconfiguration data without disturbing other portions of the memory cell array. The memory cells may be loaded with configuration data on an integrated circuit such as a programmable logic device. Memory cell outputs may configure programmable logic. To avoid disturbing programmable logic operations for programmable logic that is unaffected by the reconfigured cells during reconfiguration, unaffected memory cells are not unnecessarily cleared. Only those memory cells that need to be cleared to conform to the new configuration data that is being loaded into the array need to be loaded with logic zero values during reconfiguration operations. After these clearing operations are complete, set operations may be performed to convert appropriate memory cells to logic one values to match the new configuration data.

Claims

1. Memory circuitry, comprising:

an array of memory cells, wherein each memory cell has associated first and second data lines; and

control circuitry that selectively loads new data into a given set of the memory cells in place of old data by maintaining the first and second data lines for a first part of the given set of the memory cells at a given logic value while the given set of memory cells is addressed so that the old data in the first part of the given set of memory cells is undisturbed and by maintaining the first and second data lines for a second part of the given set of memory cells at respective complementary logic values while the given set of memory cells is addressed.

2. The memory circuitry defined in claim 1 wherein the control circuitry comprises first and second lines that receive clear and set signals, respectively.

3. The memory circuitry defined in claim 1 wherein the given logic value comprises a logic one value and wherein the control circuitry is configured to hold the first and second data lines for the first part of the given set of memory cells at the logic one value while the given set of memory cells is addressed so that the first part of the given set of memory cells is undisturbed.

4. The memory circuitry defined in claim 1 wherein each memory cell comprises:

first and second address transistors that receive an address signal from an associated address line; and

first and second cross-coupled inverters, wherein in each memory cell, one of the first data lines is connected to an input of the first inverter by the first address transistor and one of the second data lines is connected to an input of the second inverter by the second address transistor.

5. The memory circuitry defined in claim 1 wherein each memory cell in the array of memory cells comprises an output, wherein the array of memory cells contains configuration data, and wherein the outputs of the memory cells provide static control signals based on the configuration data that configure programmable logic.

6. The memory circuitry defined in claim 1, wherein the control circuitry comprises an input that receives the new data in a configuration data bitstream and produces corresponding signals on the first and second data lines to selectively reconfigure the array of memory cells by leaving the first part of the given set of memory cells undisturbed while reconfiguring the second part of the given set of memory cells based on the new data in the configuration data bitstream.

7. The memory circuitry defined in claim 1 wherein the control circuitry comprises:

configuration control circuitry that produces set and clear control signals; and

data line circuitry that provides logic signals to the first and second data lines in response to the set and clear control signals.

8. The memory circuitry defined in claim 7 wherein each memory cell in the array of memory cells comprises an output, wherein the outputs of the memory cells provide static control signals based on data values loaded into the memory cells, and wherein the outputs configure programmable logic on a programmable logic device that contains the array of memory cells.

9. A programmable logic device, comprising:

programmable logic;

an array of memory cells, wherein the memory cells are loaded with configuration data and supply corresponding output signals that configure the programmable logic to implement a custom circuit; and

circuitry that is configured to perform partial reconfiguration operations on the array of memory cells in which memory cells are only cleared when those memory cells remain cleared during normal operation of the programmable logic device following completion of the partial reconfiguration operations.

10. The programmable logic device defined in claim 9 wherein the array of memory cells comprises rows and columns of memory cells and wherein the circuitry is configured to perform the partial reconfiguration operations on only a set of the memory cells that are not arranged in a rectangular block.

11. The programmable logic device defined in claim 9 wherein each memory cell in the array of memory cells comprises:

first and second address transistors with which the circuitry addresses the memory cells during the partial reconfiguration operations; and

a first data line and a second data line that are respectively coupled to the memory cell through the first and second address transistors.

12. The programmable logic device defined in claim 11 wherein the circuitry is configured to clear some of the memory cells during partial reconfiguration operations by holding the first data lines of those memory cells at a given logic value while holding the second data lines of those memory cells at a logic value that is complementary to the given logic value.

13. The programmable logic device defined in claim 12 wherein the circuitry is configured to set some of the memory cells during partial reconfiguration operations by holding the first data lines of those memory cells at the logic value that is complementary to the given logic value while holding the second data lines of those memory cells at the given logic value.

14. The programmable logic device defined in claim 13 wherein the circuitry is configured to leave some of the memory cells undisturbed during partial reconfiguration operations by holding the first and second data lines of those memory cells at the given logic value during partial reconfiguration operations.

15. The programmable logic device defined in claim 14 wherein the circuitry comprises:

configuration control circuitry that produces set and clear control signals; and

data line circuitry that provides logic signals to the first and second data lines in response to the set and clear control signals.

16. A method for performing a reconfiguration operation on an array of memory cells so that in a set of the memory cells old configuration data is replaced with new configuration data, the method comprising:

as part of the reconfiguration operation, loading a first portion of the set of memory cells with a given logic value without disturbing a second portion of the set of memory cells that is different than the first portion, wherein the given logic value loaded into the first portion of the set of memory cells represents the new configuration data for the first portion of the set of memory cells; and

as part of the reconfiguration operation and after loading the first portion of the set of memory cells with the given logic value, loading the second portion of the set of memory cells with a complement to the given logic value, wherein the complement to the given logic value represents the new configuration data for the second portion of the set of memory cells.

17. The method defined in claim 16 wherein loading the first portion of the set of memory cells comprises loading a logic zero into each of the memory cells in the first portion of memory cells to clear the first portion of the set of memory cells without disturbing the second portion of the set of memory cells.

18. The method defined in claim 17 wherein loading the second portion of the set of memory cells comprises loading a logic one into each of the memory cells in the second portion of the memory cells.

19. The method defined in claim 17 wherein the set of memory cells comprises a subset of the array of memory cells, wherein loading the second portion of the set of memory cells comprises loading a logic one into each of the memory cells in the second portion of the memory cells without disturbing the first portion of the set of memory cells and without disturbing any memory cells in the array of memory cells other than the subset of memory cells.

20. The method defined in claim 16 wherein the array of memory cells comprises an array of configuration random-access memory cells on a programmable logic device that has programmable logic, wherein the configuration random-access memory cells have respective outputs at which static control signals are applied to the programmable logic to configure the programmable logic, the method further comprising operating a portion of the programmable logic without interruption during the reconfiguration operation.

21. A method for reconfiguring a subset of an array of configuration data memory cells on a programmable integrated circuit by replacing old configuration data in the subset of configuration data memory cells with new configuration data without disturbing configuration data memory cells in the array that are loaded with configuration data that is not to be reconfigured, comprising:

during reconfiguration, clearing only those configuration data memory cells in the subset that are to receive a logic zero value in the new configuration data.

22. The method defined in claim 21 further comprising:

after clearing all of the configuration data memory cells in the subset that are to receive a logic zero value during reconfiguration, setting all of the configuration data memory cells in the subset that are to receive a logic one value during reconfiguration to a logic one value.

23. The method defined in claim 22, wherein clearing and setting of the configuration data memory cells comprises adjusting signal values on first and second data lines in the array in response to clear and set signals provided from control circuitry while addressing the subset of configuration data memory cells.

24. A method for performing a reconfiguration operation on programmable elements in a programmable logic device so that in a given set of the programmable elements old configuration data is replaced with new configuration data, the method comprising:

in a first phase, selectively clearing a first part of the given set of programmable elements; and

in a second phase, selectively setting a second part of the given set of programmable elements.

25. The method defined in claim 24, wherein selectively clearing the first part of the given set of programmable elements comprises loading configuration data into the given set of programmable elements that is a logical AND of the old configuration data and the new configuration data.

26. The method defined in claim 25, wherein selectively setting the second part of the given set of programmable elements comprises loading the new configuration data into the given set of programmable elements.

27. The method defined in claim 24, wherein selectively clearing the first part of the given set of programmable elements comprises selectively clearing a rectangular array of the programmable elements.

28. The method defined in claim 24, wherein selectively clearing the first part of the given set of programmable elements comprises using data lines and complementary data lines to clear the first part of the given set of programmable elements.

29. The method defined in claim 24, wherein selectively clearing comprises loading a first set of configuration data that specifies which of the programmable elements are to be selectively cleared and wherein selectively setting comprises loading a second set of configuration data that specifies which of the programmable elements are to be selectively set.

30. The method defined in claim 24, wherein selectively clearing and selectively setting comprise:

loading a configuration data, wherein selectively clearing comprises clearing programmable elements that correspond to zeros in the configuration data, and wherein selectively setting comprises setting programmable elements that correspond to ones in the configuration data.