Memory module decoder
First Claim
1. A circuit configured to be mounted on a memory module so as to be electrically coupled to a first number of double-data-rate (DDR) memory devices arranged in a first number of ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals corresponding to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit comprising:
- a logic element configurable to receive the set of input signals;
a register; and
a phase-lock loop circuit configurable to be operatively coupled to the first number of DDR memory devices, the logic element, and the register,wherein the circuit is configurable to generate a set of output signals in response to the set of input signals, the set of output signals corresponding to the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit is configurable to further respond to the set of input signals from the computer system by generating and transmitting the set of output signals to the first number of DDR memory devices.
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0 Petitions
Reexamination
Accused Products
Abstract
A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.
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Citations
20 Claims
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1. A circuit configured to be mounted on a memory module so as to be electrically coupled to a first number of double-data-rate (DDR) memory devices arranged in a first number of ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals from the computer system, the set of input signals comprising row/column address signals, bank address signals, and chip-select signals, the set of input signals corresponding to a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit comprising:
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a logic element configurable to receive the set of input signals; a register; and a phase-lock loop circuit configurable to be operatively coupled to the first number of DDR memory devices, the logic element, and the register, wherein the circuit is configurable to generate a set of output signals in response to the set of input signals, the set of output signals corresponding to the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit is configurable to further respond to the set of input signals from the computer system by generating and transmitting the set of output signals to the first number of DDR memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A circuit configured to be mounted on a memory module so as to be electrically coupled to a first number of double-data-rate (DDR) memory devices arranged in a first number of ranks on the memory module, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals from the computer system, the set of input signals comprising at least one row/column address signal, bank address signals, and at least one chip-select signal, the set of input signals configured to control a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit comprising:
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a logic element configurable to receive the set of input signals; a register; and a phase-lock loop circuit configurable to be operatively coupled to the first number of DDR memory devices, the logic element, and the register, wherein the circuit is configurable to generate a set of output signals in response to the set of input signals, the set of output signals configured to control the first number of DDR memory devices arranged in the first number of ranks, wherein the circuit is configurable to transmit the set of output signals to the first number of DDR memory devices. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A circuit configured to be mounted on a memory module so as to be electrically coupled to a first number of double-data-rate (DDR) memory devices arranged in a first number of ranks on the memory module, the first number of ranks selectable by a first number of chip-select signals, the memory module configured to be electrically coupled to a memory controller of a computer system so as to receive a set of input signals from the computer system, the set of input signals comprising row address signals, column address signals, bank address signals, and a second number of chip-select signals less than the first number of chip-select signals, the set of input signals configured to utilize a second number of DDR memory devices arranged in a second number of ranks, the second number of DDR memory devices smaller than the first number of DDR memory devices and the second number of ranks less than the first number of ranks, the circuit comprising:
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a logic element configurable to receive the set of input signals; a register; and a phase-lock loop circuit configurable to be operatively coupled to the first number of DDR memory devices, the logic element, and the register, wherein the circuit is configurable to generate a set of output signals in response to the set of input signals, the set of output signals comprising the first number of chip-select signals and configured to utilize the first number of DDR memory devices arranged in the first number of ranks. - View Dependent Claims (20)
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Specification