On chip MOS transmit / receive switch

• US 7,865,149 B2
• Filed: 06/14/2007
• Issued: 01/04/2011
• Est. Priority Date: 06/01/2007
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya Reza, Han, Yiping
• Primary Examiner(s): NGUYEN, SIMON
• Application Number:
  US11/762,790
• Publication Number:
  US 20080299913A1
• Time in Patent Office: 1,300 Days
• Field of Search: 455/78, 455/80, 455/82, 455/83, 455/88, 455/333, 455/550.1, 455/552.1, 455/553.1
• US Class Current: 455/73
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

On-chip MOS circuitry couples a communication path between an output stage amplifier and an output port and disables a circuit path between an input amplifier and the output port by creating a high impedance circuit during transmit operations. Alternatively, the circuitry opens the transmit circuit path with an isolated MOSFET and enables the second circuit path by creating an impedance matched circuit. The switch is formed within an isolated region to allow it to float with a signal to avoid breakdown. This floating MOS switch can be used for a variety of other applications in addition to its use as a transmit/receive switch even though formed on the same die as the communication circuitry.

Claims

1. An integrated circuit transceiver, comprising:

baseband processor for generating outgoing data and for processing ingoing data;

analog front end for producing an outgoing RF signal from the outgoing data and for producing the ingoing data from a received ingoing RF signal;

a power amplifier operably coupled to receive the outgoing RF signal to produce a power amplified outgoing RF signal;

a radio frequency port for transmitting the power amplified outgoing RF signal and for receiving the ingoing RF signal;

an on chip CMOS transmit-receive module operably coupled between the power amplifier and antenna on a transmit path and between the RF front end and the radio frequency port on a receive path;

logic for producing a transmit-receive mode indication to the transmit-receive module to prompt the transmit-receive module to be configured in to a corresponding transmit or receive mode, wherein the transmit-receive module, based upon the mode indication, generates first and second bias signals to first and second wells formed about a MOSFET switch to create reverse biased junction across the boundary between the first and second wells and between the second well and one of a third well or substrate having a common boundary with the second well; and

wherein the transmit-receive module further comprises switching circuitry for;

during the transmit mode, closing a connection between the power amplifier and the antenna and for creating a high impedance circuit between the analog front end receive path and the radio frequency port; and

during the receive mode, opening the connection between the power amplifier and the radio frequency port and for creating a low impedance circuit between the analog front end receive path and the radio frequency port.

2. The integrated circuit transceiver of claim 1 wherein the switching circuitry comprises a MOSFET formed within a plurality of wells within a substrate.

3. The integrated circuit transceiver of claim 2 wherein each of the plurality of wells is biased by a supply to create a reversed bias diode between the boundaries of the wells and substrate to create a capacitive device between the wells and substrate at the boundaries.

4. The integrated circuit transceiver of claim 3 further including a large resistive element operably coupled between the supply and the plurality of wells.

5. The integrated circuit transceiver of claim 2 wherein the MOSFET is an N-type MOSFET, a first well within which the MOSFET is formed is a P-type well and a second well within which the first well is formed is an N-type well.

6. The integrated circuit transceiver of claim 5 wherein the second well forms an outer boundary with the substrate of the integrated circuit.

7. The integrated circuit transceiver of claim 5 further comprising a third well oppositely doped in relation to the second well wherein the second well is formed within the third well.

8. The integrated circuit transceiver of claim 1 wherein the radio frequency port comprises an antenna.

9. The integrated circuit transceiver of claim 1 wherein the radio frequency port comprises a communication port coupled to a wired transmission line for a high power wired communication.

10. An integrated circuit transceiver, comprising:

baseband processor for generating outgoing data and for processing ingoing data;

analog front end for producing an outgoing RF signal from the outgoing data and for producing the ingoing data from a received ingoing RF signal;

a power amplifier operably coupled to receive the outgoing RF signal to produce a power amplified outgoing RF signal;

an antenna for transmitting the power amplified outgoing RF signal and for receiving the ingoing RF signal;

an on chip CMOS transmit-receive module operably coupled between the power amplifier and antenna on a transmit path and between the analog front end and the antenna on a receive path;

logic for producing a transmit-receive mode indication to the transmit-receive module to prompt the transmit-receive module to be configured in to a corresponding transmit or receive mode;

wherein the transmit-receive module further comprises;

an impedance block including an inductive element disposed between parallel coupled capacitive elements wherein the impedance block is operably disposed between the antenna and the analog front end and the antenna;

first switching circuitry operably disposed to short one of the parallel coupled capacitive elements based upon the transmit-receive mode indication; and

second switching circuitry operably disposed to couple the power amplifier to the antenna based upon the transmit-receive mode indication;

wherein the first switching circuitry shorts one of the capacitive elements to create a high impedance path between the antenna and the receive path of the analog front end and a wherein the second switching circuitry creates low impedance connection between the power amplifier and the antenna during a transmit mode of operation based upon the transmit-receive mode indication; and

wherein the first switching circuitry operably disposed across the one of the capacitive elements is opened to create an impedance match between the antenna and the receive path of the analog front end and a wherein the second switching circuitry creates an open connection between the power amplifier and the antenna during a receive mode of operation based upon the transmit-receive mode indication.

11. The integrated circuit transceiver of claim 10 wherein at least one of the first and second switching circuitry comprises a MOSFET formed within a first well that is further formed within a second well that is further formed within a substrate.

12. The integrated circuit transceiver of claim 11 wherein each of the first and second wells is biased to create a reversed bias diode between the boundaries of the first and second wells and between the second well and the substrate.

13. The integrated circuit transceiver of claim 12 further including a large resistive element operably coupled between each of the first and second wells and a corresponding bias signal.

14. The integrated circuit transceiver of claim 13 wherein the bias signal provided to second well has a greater magnitude that the bias signal for the first well.

15. The integrated circuit transceiver of claim 13 wherein the bias signal provided to second well has a magnitude that is greater than or equal to 1.5 volts and wherein the bias signal for the first well is less than or equal to one volt.

16. The integrated circuit transceiver of claim 11 wherein the MOSFET is an N-type MOSFET, the first well is a P-type well and the second well is an N-type well.

17. The integrated circuit transceiver of claim 11 further comprising a third well oppositely doped from the second well wherein the second well is formed within the third well.

18. An integrated circuit transceiver, comprising:

a first communication circuit;

a second communication circuit;

communication selection switch circuitry coupled to the first and second communication circuits, the communication selection switch circuitry comprising at least one isolated MOSFET device operable to perform specified switching and is further operable to selectively isolate the first communication circuit from the second communication circuit, the communication selection switch circuitry generating first and second bias signals to first and second wells formed about a MOSFET switch to create reverse biased P-N junction across the boundary between the first and second wells and between the second well and one of a third well or substrate having a common boundary with the second well; and

wherein the communication selection switch circuitry and the first and second communication circuits are all formed on the same dielectric substrate.

19. The integrated circuit transceiver of claim 18 wherein at least one of the first and second communication circuits is operable to produce a signal that exceeds a breakdown voltage of the at least one isolated MOSFET device.

20. The integrated circuit transceiver of claim 18 wherein at least one of the first and second communication circuits comprises one of a transmit path communication circuit, a tuning circuit, or a signal generator circuit, or an amplification circuit.

21. The integrated circuit transceiver of claim 18 wherein the communication selection switch circuitry is operable to select between multiple transmit paths.

22. The integrated circuit transceiver of claim 18 wherein the communication selection switch circuitry is operable to select between multiple receive paths.

23. The integrated circuit transceiver of claim 18 wherein the communication selection switch circuitry is operable to select between multiple transmit paths and multiple receive paths.

24. A method for delivering a power amplified outgoing radio frequency signal to an antenna during a transmit mode of operation and for delivering an in-going radio frequency signal to receive path of an analog front end, comprising:

generating first and second bias signals to first and second wells formed about a MOSFET switch to create reverse biased P-N junction across the boundary between the first and second wells and between the second well and one of a third well or substrate having a common boundary with the second well;

generating a first of two control signals to create a high impedance circuit between an antenna and a first port of a transmit-receive module and a low impedance connection between the antenna and a second port of the transmit-receive module during a first mode of operation;

generating the second of the two control signals to create a low impedance circuit between the antenna and the first port of a transmit-receive module and a high impedance connection between the antenna and the second port of the transmit-receive module during a second mode of operation; and

generating an amplified outgoing RF signal to one of the first and second ports while the first control signal is being generated and receiving an ingoing RF signal from one of the first and second ports while the second control signal is being generated.

25. The method of claim 24 further including shorting a capacitive element to create the high impedance circuit.

26. The method claim 24 further including operably coupling a capacitive element to create the low impedance circuit.

27. The method of claim 24 wherein the MOSFET switch electrically floats within the outgoing RF signal.

28. The method of claim 27 wherein the MOSFET is a small scale device and whereby large magnitude outgoing RF signals do not create a break down condition for the MOSFET as the switch electrically floats with the outgoing RF signal.