Configuring floating point operations in a programmable logic device

• US 7,865,541 B1
• Filed: 01/22/2007
• Issued: 01/04/2011
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Malzahn; David H
• Application Number:
  US11/625,655
• Time in Patent Office: 1,443 Days
• Field of Search: None
• US Class Current: 708/204
• CPC Class Codes: G06F 2207/3832 Less usual number representations
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/485 Adding; Subtracting G06F7/4833, G06F7/4836 take precedence
• CPC Class Codes: G06F 7/4876 Multiplying
• CPC Class Codes: H03M 7/02 Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word

Abstract

A programmable logic device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.

Claims

1. A method of configuring a programmable logic device to perform floating point operations on input values formatted in accordance with a standard requiring normalized values having a first mantissa size and a first exponent size, said method comprising:

configuring logic of said programmable logic device to reformat said input values to have a second mantissa size larger than said first mantissa size without normalization;

configuring logic of said programmable logic device to perform said operations on said reformatted values to compute a result without normalization; and

configuring logic of said programmable logic device to reformat said result to a normalized value in accordance with said standard having said first mantissa size.

2. The method of claim 1 wherein:

said reformatting said values further comprises reformatting to a second exponent size larger than said first exponent size; and

said reformatting said result further comprises reformatting to said first exponent size.

3. The method of claim 2 wherein:

in said standard format, negative numbers are represented in two'"'"'s-complement format;

in said method, negative numbers are represented in one'"'"'s-complement format; and

when a first number of said floating point operations are clustered and a second number out of said first number of operations produces a negative number, said reformatting said result further comprises adding a value equal to said second number to said result.

4. The method of claim 2 wherein:

said mantissa of each said value formatted in accordance with said standard has an implied leading bit; and

said reformatting said values comprises making said implied leading bit explicit.

5. The method of claim 4 wherein:

said reformatting said values comprises adding at least one of (a) a first number of leading zeroes, and (b) a second number of trailing zeroes;

whereby;

conditions that would be one of (1) an underflow, and (2) an overflow, are avoided.

6. The method of claim 5 wherein said first number and said second number are equal.

7. The method of claim 5 wherein said first and second numbers are selected in accordance with said operations to avoid one of (a) an underflow, and (b) an overflow.

8. The method of claim 4 further comprising:

configuring logic of said programmable logic device to normalize said reformatted values, after performing a first portion of said operations, to avoid one of (a) an underflow, and (b) an overflow; and

configuring logic of said programmable logic device to continue said performing after said normalizing.

9. The method of claim 4 further comprising:

configuring logic of said programmable logic device to normalize said reformatted values, after performing a first portion of said operations, to accommodate an operation in hardware of said programmable logic device in accordance with said standard; and

configuring logic of said programmable logic device to continue said performing after said normalizing and after said operation in said hardware.

10. The method of claim 9 wherein said hardware is a dedicated multiplier.

11. A programmable logic device configured to perform floating point operations on input values formatted in accordance with a standard requiring normalized values having a first mantissa size and a first exponent size, said configured programmable logic device comprising:

logic configured to reformat said input values to have a second mantissa size larger than said first mantissa size without normalization;

logic configured to perform said operations on said reformatted values to compute a result without normalization; and

logic configured to reformat said result to a normalized value in accordance with said standard having said first mantissa size.

12. The configured programmable logic device of claim 11 wherein:

said logic configured to reformat said values is further configured to reformat to a second exponent size larger than said first exponent size; and

said logic configured to reformat said result is further configured to reformat to said first exponent size.

13. The configured programmable logic device of claim 12 wherein:

in said standard format, negative numbers are represented in two'"'"'s-complement format;

in said programmable logic device, negative numbers are represented in one'"'"'s-complement format; and

when a first number of said floating point operations are clustered and a second number out of said first number of operations produces a negative number, said logic configured to reformat said result is further configured to add a value equal to said second number to said result.

14. The configured programmable logic device of claim 12 wherein:

said mantissa of each said value formatted in accordance with said standard has an implied leading bit; and

said logic configured to reformat said values is programmed to make said implied leading bit explicit.

15. The configured programmable logic device of claim 14 wherein:

said logic configured to reformat said values is configured to add at least one of (a) a first number of leading zeroes, and (b) a second number of trailing zeroes;

whereby;

conditions that would be one of (1) an underflow, and (2) an overflow, are avoided.

16. The configured programmable logic device of claim 15 wherein said first number and said second number are equal.

17. The configured programmable logic device of claim 15 wherein said first and second numbers are selected in accordance with said operations to avoid one of (a) an underflow, and (b) an overflow.

18. The configured programmable logic device of claim 14 further comprising:

logic configured to normalize said reformatted values after performing a first portion of said operations, to avoid one of (a) an underflow, and (b) an overflow; and

logic configured to continue said performing after said normalizing.

19. The configured programmable logic device of claim 14 further comprising:

dedicated hardware for performing at least a portion of said operations.

20. The configured programmable logic device of claim 19 wherein said dedicated hardware is a dedicated multiplier.

21. The configured programmable logic device of claim 20 wherein said dedicated multiplier is sized at least as large as said second mantissa size.

22. The configured programmable logic device of claim 21 further comprising:

logic configured to normalize said reformatted values after performing a first portion of said operations prior to said dedicated multiplier; and

logic configured to continue said performing after said normalizing.

23. The configured programmable logic device of claim 19 wherein said dedicated hardware is sized at least as large as said second mantissa size.

24. The configured programmable logic device of claim 23 further comprising:

logic configured to normalize said reformatted values after performing a first portion of said operations prior to said dedicated hardware; and

logic configured to continue said performing after said normalizing.

25. A machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable logic device to execute a method of performing floating point operations on input values formatted in accordance with a standard requiring normalized values having a first mantissa size and a first exponent size, said instructions comprising:

instructions to configure logic to reformat said input values to have a second mantissa size larger than said first mantissa size without normalization;

instructions to configure logic to perform said operations on said reformatted values to compute a result without normalization; and

instructions to configure logic to reformat said result to a normalized value in accordance with said standard having said first mantissa size.

26. The machine-readable data storage medium of claim 25 wherein:

said instructions to configure logic to reformat said values configures said logic to reformat to a second exponent size larger than said first exponent size; and

said instructions to configure logic to reformat said result configures said logic to reformat to said first exponent size.

27. The machine-readable data storage medium of claim 26 wherein:

in said standard format, negative numbers are represented in two'"'"'s-complement format;

in said method, negative numbers are represented in one'"'"'s-complement format; and

when a first number of said floating point operations are clustered and a second number out of said first number of operations produces a negative number, said instructions to configure logic to reformat said result further comprise instructions to add a value equal to said second number to said result.

28. The machine-readable data storage medium of claim 26 wherein:

said mantissa of each said value formatted in accordance with said standard has an implied leading bit; and

said instructions to configure logic to reformat said values configures said logic to make said implied leading bit explicit.

29. The machine-readable data storage medium of claim 28 wherein:

said instruction to configure logic to reformat said values configures said logic to add at least one of (a) a first number of leading zeroes, and (b) a second number of trailing zeroes;

whereby;

conditions that would be one of (1) an underflow, and (2) an overflow, are avoided.

30. The machine-readable data storage medium of claim 29 wherein said first number and said second number are equal.

31. The machine-readable data storage medium of claim 29 wherein said first and second numbers are selected in accordance with said operations to avoid one of (a) an underflow, and (b) an overflow.

32. The machine-readable data storage medium of claim 28 further comprising:

instruction to configure logic to normalize said reformatted values after performing a first portion of said operations, to avoid one of (a) an underflow, and (b) an overflow; and

instructions to configure logic to continue said performing after said normalizing.

33. The machine-readable data storage medium of claim 28 wherein said programmable logic device comprises a dedicated multiplier for performing at least a portion of said operations and said dedicated multiplier is sized smaller than said second mantissa size, said data storage medium further comprising:

instructions to configure logic to normalize said reformatted values after performing a first portion of said operations prior to said dedicated multiplier; and

instructions to configure logic to continue said performing after said normalizing.

34. The machine-readable data storage medium of claim 28 wherein said programmable logic device comprises dedicated hardware for performing at least a portion of said operations and said dedicated hardware is sized smaller than said second mantissa size, said data storage medium further comprising:

instructions to configure logic to normalize said reformatted values after performing a first portion of said operations prior to said dedicated hardware; and

instructions to configure logic to continue said performing after said normalizing.