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Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage

  • US 7,865,630 B2
  • Filed: 04/20/2009
  • Issued: 01/04/2011
  • Est. Priority Date: 12/02/2003
  • Status: Expired due to Fees
First Claim
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1. A parity dual-mode switch comprising:

  • an upstream interface to a host bus for connecting to a host;

    a plurality of downstream interfaces connecting to a plurality of memory blocks;

    a virtual bridge for connecting the upstream interface to the plurality of downstream interfaces;

    a transaction manager, coupled to control the virtual bridge to act as a hub by passing data packets from the host to the plurality of memory blocks through the virtual bridge when operating in a hub mode, and for acting as a single endpoint to the host when operating in a single-endpoint mode;

    a virtual storage processor, coupled to the transaction manager, wherein the virtual storage processor further stripes the data from the host into data segments across multiple endpoints for storage in multiple downstream memory blocks in the plurality of memory blocks;

    a parity and Error-Correction Code (ECC) circuit for correcting errors occurring in data segments in a stripe read from one of the plurality of memory blocks acting as an endpoint wherein the parity and ECC circuit is also for generating parity bits for storage with the data segments for redundant storage;

    wherein the transaction manager passes data between the host and the plurality of memory blocks and intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

    wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode;

    wherein the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks; and

    mode logic, coupled to the transaction manager, for determining when to set the transaction manager in the hub mode and when to set the transaction manager in the single-endpoint mode.

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