Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage

• US 7,865,630 B2
• Filed: 04/20/2009
• Issued: 01/04/2011
• Est. Priority Date: 12/02/2003
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, I-Kang Frank, Ma, Abraham C., Lee, Charles C.
• Primary Examiner(s): CHEN, ALAN S
• Application Number:
  US12/426,378
• Publication Number:
  US 20090204732A1
• Time in Patent Office: 624 Days
• Field of Search: None
• US Class Current: 710/14
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Claims

1. A parity dual-mode switch comprising:

an upstream interface to a host bus for connecting to a host;

a plurality of downstream interfaces connecting to a plurality of memory blocks;

a virtual bridge for connecting the upstream interface to the plurality of downstream interfaces;

a transaction manager, coupled to control the virtual bridge to act as a hub by passing data packets from the host to the plurality of memory blocks through the virtual bridge when operating in a hub mode, and for acting as a single endpoint to the host when operating in a single-endpoint mode;

a virtual storage processor, coupled to the transaction manager, wherein the virtual storage processor further stripes the data from the host into data segments across multiple endpoints for storage in multiple downstream memory blocks in the plurality of memory blocks;

a parity and Error-Correction Code (ECC) circuit for correcting errors occurring in data segments in a stripe read from one of the plurality of memory blocks acting as an endpoint wherein the parity and ECC circuit is also for generating parity bits for storage with the data segments for redundant storage;

wherein the transaction manager passes data between the host and the plurality of memory blocks and intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode;

wherein the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks; and

mode logic, coupled to the transaction manager, for determining when to set the transaction manager in the hub mode and when to set the transaction manager in the single-endpoint mode.

2. The parity dual-mode switch of claim 1 further comprising:

a striping unit for distributing data segments of equal size across multiple endpoints of the plurality of memory blocks;

a flash memory page ECC circuit for detecting and correcting errors occurring inside a flash memory page, wherein ECC codes are stored in a flash page spare area, wherein the ECC codes are implemented by a Reed-Solomon method.

3. A caching dual-mode switch comprising:

an upstream interface to a host bus for connecting to a host;

a plurality of downstream interfaces connecting to a plurality of memory blocks;

a virtual bridge for connecting the upstream interface to the plurality of downstream interfaces;

a transaction manager, coupled to control the virtual bridge to act as a hub by passing data packets from the host to the plurality of memory blocks through the virtual bridge when operating in a hub mode, but for acting as a single endpoint to the host when operating in a single-endpoint mode;

a caching circuit, implemented by a volatile memory to store associated buffer data from the upstream interface, the caching circuit for transaction buffering and packet re-ordering;

a virtual storage processor, coupled to the transaction manager, wherein the virtual storage processor further stripes the host data into data segments across multiple endpoints for storage in multiple downstream memory blocks;

wherein the transaction manager passes data between the host and the plurality of memory blocks and intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode;

wherein the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks; and

mode logic, coupled to the transaction manager, for determining when to set the transaction manager in the hub mode and when to set the transaction manager in the single-endpoint mode.

4. The caching dual-mode switch of claim 3 further comprising:

a striping unit for distributing data segments of equal size across multiple endpoints of the plurality of memory blocks;

a flash data buffer, coupled to the virtual bridge, for matching a bus width of internal flash buses, wherein the bus width is 32 bits or 64 bits.

5. A wear-leveling dual-mode switch comprising:

an upstream interface to a host bus for connecting to a host;

a plurality of downstream interfaces connecting to a plurality of memory blocks;

a virtual bridge for connecting the upstream interface to the plurality of downstream interfaces;

a transaction manager, coupled to control the virtual bridge to act as a hub by passing data packets from the host to the plurality of memory blocks through the virtual bridge when operating in a hub mode, but for acting as a single endpoint to the host when operating in a single-endpoint mode;

a caching circuit, implemented by a volatile memory to store associated buffer data from the upstream interface, the caching circuit for transaction buffering and packet re-ordering;

a virtual storage processor, coupled to the transaction manager, wherein the virtual storage processor further stripes the host data into data segments across multiple endpoints for storage in the plurality of memory blocks;

a flash memory controller, coupled to the plurality of memory blocks, for wear leveling data written to the plurality of memory blocks for even wear across flash storage blocks;

wherein the transaction manager passes data between the host and the plurality of memory blocks but intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode;

wherein the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks; and

mode logic, coupled to the transaction manager, for determining when to set the transaction manager in the hub mode and when to set the transaction manager in the single-endpoint mode.

6. The wear-leveling dual-mode switch of claim 5 further comprising:

a striping unit for distributing data segments of equal size across multiple endpoints of the plurality of memory blocks for providing wear-leveling.

7. A mapping dual-mode switch comprising:

an upstream interface to a host bus for connecting to a host;

a plurality of downstream interfaces connecting to a plurality of memory blocks;

a virtual bridge for connecting the upstream interface to the plurality of downstream interfaces;

a transaction manager, coupled to control the virtual bridge to act as a hub by passing data packets from the host to the plurality of memory blocks through the virtual bridge when operating in a hub mode, but for acting as a single endpoint to the host when operating in a single-endpoint mode;

a caching circuit, implemented by a volatile memory to store associated buffer data from the upstream interface, the caching circuit for transaction buffering and packet re-ordering;

a virtual storage processor, coupled to the transaction manager, wherein the virtual storage processor further stripes the host data into data segments across multiple endpoints for storage in multiple downstream memory blocks;

wherein the virtual storage processor further comprises means for mapping the host data into data segments of equal size across multiple endpoints for storage in the plurality of memory blocks;

wherein the transaction manager passes data between the host and the plurality of memory blocks and intercepts and modifies packets from the host to generate secondary packets over the bus segments to the plurality of memory blocks when operating in the single-endpoint mode;

wherein the plurality of memory blocks and the bus segments are hidden from the host by the transaction manager when operating in the single-endpoint mode, but visible as endpoints to the host when operating in hub mode;

wherein the dual-mode switch operates in modes having multiple endpoints or a single endpoint for multiple downstream memory blocks; and

mode logic, coupled to the transaction manager, for determining when to set the transaction manager in the hub mode and when to set the transaction manager in the single-endpoint mode.

8. The mapping dual-mode switch of claim 7 further comprising:

a striping unit for distributing data segments of equal size across multiple endpoints of the plurality of memory blocks;

a flash memory controller for mapping data written to the plurality of memory blocks for distribution across flash storage blocks.