Sharing of functions between an embedded controller and a host processor

• US 7,865,646 B1
• Filed: 07/20/2006
• Issued: 01/04/2011
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kirschner, Yuval, Friedman, Yehezkel, Flachs, Victor, Falik, Ohad
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): Huynh; Kim T
• Application Number:
  US11/490,008
• Time in Patent Office: 1,629 Days
• Field of Search: 710/107, 710/200, 710301-306, 710240-244, 713/600, 713/300, 713/324
• US Class Current: 710/200
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

Claims

1. A system for allowing shared access by at least first and second processors to a module, the system comprising:

a main power supply and an alternative power supply, wherein at least part of the module is configured to be powered by the alternative power supply;

an internal bus connected to both (i) the at least part of the module configured to be powered by the alternative power supply and (ii) at least part of the module configured to be powered by the main power supply;

a first processor interface associated with the first processor and configured to be powered by the main power supply and a second processor interface associated with the second processor and configured to be powered by the alternative power supply; and

a transaction control module configured to determine that the main power supply is off and prevent the second processor from accessing the at least part of the module configured to be powered by the main power supply when the main power supply is off;

wherein, even when the main power supply is off, at least one of the processors is capable configured to access, through the bus, the at least part of the module that is configured to be powered by the alternative power supply.

2. The system of claim 1, further comprising:

a domain separator configured to isolate the at least part of the module that is configured to be powered by the main power supply from the at least part of the module that is configured to be powered by the alternative power supply when the main power supply is off.

3. The system of claim 1, further comprising:

a main power on detect circuit configured to detect if the main power supply is within a specified active range.

4. The system of claim 1, further comprising:

a generator configured to generate a reset select signal;

wherein the reset select signal identifies one of an alternative power up reset and a main power up reset for resetting at least one bit associated with the alternative power supply.

5. The system of claim 4, wherein the at least one bit associated with the alternative power supply is a content lock bit.

6. The system of claim 5, wherein the content lock bit indicates whether the content lock bit and any associated protected bits are locked, and further comprising:

at least one unlock bit indicating a reset of the at least one content lock bit.

7. The system of claim 6, wherein the second processor is configured to control the at least one unlock bit.

8. The system of claim 4, wherein the generator is associated with at least one reset select bit.

9. The system of claim 8, wherein the second processor is configured to control the at least one reset select bit.

10. The system of claim 1, wherein the module is part of an input/output chip.

11. The system of claim 1, further comprising an extension bus configured to be powered by the alternative power supply;

wherein the module is configured to be accessed via the extension bus.

19. The system of claim 1, wherein:

the processors include an embedded controller and a host processor; and

the module comprises one of a plurality of modules.

21. The system of claim 1, wherein the at least part of the module that is configured to be powered by the main power supply is accessible by the processors.

12. In a system comprising first and second processors coupled to at least part of a module powered by a main power supply, the first processor having a first processor interface powered by the main power supply and the second processor having a second processor interface powered by an alternative power supply, a method of preventing the second processor from accessing the at least part of the module powered by the main power supply when the main power supply is off, the method comprising the steps of:

determining that the main power supply is off;

indicating that the main power supply is off; and

preventing the second processor from accessing the at least part of the module powered by the main power supply.

13. The method of claim 12, wherein the indicating is provided to the second processor.

14. The method of claim 13, wherein the indicating is provided to the second processor if the second processor attempts to access the at least part of the module powered by the main power supply.

20. The method of claim 12, further comprising:

allowing access to at least part of the module that is configured to be powered by the alternative power supply even when the main power supply is off.

15. A system for allowing shared access by at least first and second processors to a module, comprising:

a bus coupled to at least part of the module configured to be powered by a first power supply, the bus also coupled to at least part of the module configured to be powered by a second power supply;

a first processor interface associated with the first processor and configured to be powered by the first power supply and a second processor interface associated with the second processor and configured to be powered by the second power supply, the interfaces configured to facilitate communication between the processors and the bus; and

a transaction control module configured to determine that the first power supply is off and prevent the second processor from accessing the at least part of the module powered by the first power supply when the first power supply is off.

16. The system of claim 15, further comprising:

a domain separator configured to isolate the at least part of the module that is configured to be powered by the first power supply from the at least part of the module that is configured to be powered by the second power supply; and

a power on detect circuit configured to detect if the first power supply is within a specified active range.

17. The system of claim 15, further comprising:

a generator configured to generate a reset select signal, wherein the reset select signal identifies one of a first power up reset and a second power up reset for resetting at least one bit associated with the second power supply.

18. The system of claim 15, further comprising:

an extension bus configured to be powered by the second power supply, wherein the module is configured to be accessed via the extension bus.

22. The system of claim 15, wherein the transaction control module is further configured to allow access through the bus to the at least part of the module that is configured to be powered by the second power supply when the first power supply is on and when the first power supply is off.