Multi-protocol serial interface system

• US 7,865,651 B2
• Filed: 06/29/2009
• Issued: 01/04/2011
• Est. Priority Date: 04/20/2004
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Primary Examiner(s): Myers; Paul R
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US12/494,169
• Publication Number:
  US 20090265499A1
• Time in Patent Office: 554 Days
• Field of Search: 710/305, 710/10, 713/1, 326/38
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The multi-protocol port pin array comprises a plurality of port pins which interface with an external system for exchanging data with the external system. The transport protocol change FPGA determines roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data. The pull-up change FPGA regulates pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA. The memory stores data processed in the transport protocol change FPGA unit and exchanged with the external system.

Claims

1. A multi-protocol serial interface system comprising:

a multi-protocol port pin array comprising a plurality of port pins, wherein the plurality of port pins compatibly interface with a plurality of external systems, wherein each of a plurality of the port pins is used in a plurality of serial communication methods;

a transport protocol change Field Protocol Gate Array (FPGA), wherein a plurality of different transport protocols are preconfigured with a protocol gate array logic circuit, and when one transport protocol is selected, the transport protocol change FPGA is connected with the port pins of the multi-protocol port pin array depending on the selected protocol without externally receiving an additional transport protocol; and

a pull-up change FPGA for regulating a pull-up load of the port pins connected with the transport protocol change FPGA.

2. The multi-protocol serial interface system according to claim 1, wherein roles of the port pins of the multi-protocol port pin array are changed depending on the protocol selected in the transport protocol change FPGA.

3. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA selects a protocol depending on code data stored in a plurality of coding cells.

4. The multi-protocol serial interface system according to claim 3, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.

5. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA is connected with a port pin interfacing with the external system among the port pins of the multi-protocol port pin array in response to code data stored in the plurality of coding cells.

6. The multi-protocol serial interface system according to claim 5, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.

7. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA is programmed so that input/output terminals for a power voltage and a ground voltage are fixed as a specific terminal regardless of a kind of selected protocol.

8. The multi-protocol serial interface system according to claim 1, wherein the pull-up change FPGA comprises a plurality of coding cells for storing pull-up load regulating data to regulate pull-up load of the port pins connected with the transport protocol change FPGA;

and

a load unit for regulating pull-up load of the corresponding port pins in response to the pull-up load regulating data.

9. The multi-protocol serial interface system according to claim 8, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.

10. The multi-protocol serial interface system according to claim 8, wherein the load unit is a MOS transistor for applying a power voltage to the corresponding port pin in response to the pull-up load regulating data.

11. A multi-protocol serial interface system comprising:

a multi-protocol port pin array comprising a plurality of port pins, wherein the plurality of port pins compatibly interface with a plurality of external systems, wherein each of a plurality of the port pins is used in a plurality of serial communication methods;

a plurality of protocol change FPGAs, wherein each of the protocol change FPGAs is preconfigured with a different protocol gate array logic circuit, and one of the protocol change FPGAs is selected to process data received through the port pins of the multi-protocol port pin array without externally receiving an additional transport protocol;

a plurality of registers for selectively connecting the port pins interfacing with the external system among the port pins of the multi-protocol port pin array with the selected protocol change FPGA; and

a pull-up change FPGA for regulating pull-up load of the port pins connected with the transport protocol change FPGA.

12. The multi-protocol serial interface system according to claim 11, wherein roles of the port pins of the multi-protocol port pin array are changed depending on the selected protocol change FPGA.

13. The multi-protocol serial interface system according to claim 11, wherein the protocol change FPGA is selected depending on code data stored in a plurality of coding cells.

14. The multi-protocol serial interface system according to claim 13, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.

15. The multi-protocol serial interface system according to claim 11, wherein the protocol change FPGA is programmed so that input/output terminals for a power voltage and a ground voltage are fixed as a specific terminal.

16. The multi-protocol serial interface system according to claim 11, wherein the pull-up change FPGA comprises:

a plurality of coding cells for storing pull-up load regulating data to regulate pull-up load of the port pins connected with the selected protocol change FPGA; and

a load unit for regulating pull-up load of the corresponding port pins in response to the pull-up load regulating data.

17. The multi-protocol serial interface system according to claim 16, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.

18. The multi-protocol serial interface system according to claim 16, wherein the load unit is a MOS transistor for applying a power voltage to the corresponding port pin in response to the pull-up load regulating data.