System for enhancing the memory bandwidth available through a memory module

• US 7,865,674 B2
• Filed: 08/31/2007
• Issued: 01/04/2011
• Est. Priority Date: 08/31/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Primary Examiner(s): Song; Jasmine
• Application Number:
  US11/848,309
• Publication Number:
  US 20090063784A1
• Time in Patent Office: 1,222 Days
• Field of Search: 711/5, 711/100, 711/105, 711/154, 365/189.02, 36518915-18916, 365/230.02, 365/230.05
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Claims

1. A memory system comprising:

a memory hub device integrated in a memory module;

a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module;

a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces;

a memory hub controller integrated into the memory hub device;

a link interface integrated into the memory hub device, wherein the link interface provides a communication path between the memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface;

a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller;

second multiplexer integrated into the memory hub device the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and

a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.

2. The memory system of claim 1, wherein the memory system further comprises:

a memory channel for communicating with the first set of memory devices and the second set of memory devices via the memory hub device; and

a memory controller in communication with the memory channel, wherein the memory controller generates memory access requests, receives memory access requests, and responds to memory access requests.

3. The memory system of claim 1, wherein the

memory hub controller is coupled to the first memory device data interface and the second memory device data interface.

4. The memory system of claim 3, wherein the memory hub controller responds to access request packets from one of a memory controller external to the memory module or a downstream memory hub device of another memory module by responsively driving one or more of the first set of memory devices or the second set of memory devices using a memory device address and control bus and directing one of a read data flow selector or a write data flow selector.

5. The memory system of claim 4, wherein the memory hub controller drives the read data flow selector to a multiplexer of the memory hub device to select outputting read data directly, from one of the first memory device data interface or the second memory device data interface, or outputting read data from a read data queue.

6. The memory system of claim 4, wherein the memory hub controller drives the write data flow selector to a first multiplexer and a second multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device.

7. The memory system of claim 6, wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface.

8. The memory system of claim 3, wherein the memory hub controller, in response to a write access request packet, issues a first memory write access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory write access request to the second set of memory devices via the second memory device data interface.

9. The memory system of claim 3, wherein the memory hub controller, in response to a read access request packet, issues a first memory read access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory read access request to the second set of memory devices via the second memory device data interface.

10. The memory system of claim 9, wherein read data from the first memory read access request and the second memory read access request are directly transferred to the memory controller.

11. The memory system of claim 9, wherein read data from the first memory read access request and the second memory read access request are queued prior to be transferred to the memory controller.

12. The memory system of claim 1, wherein a first memory access request is processed via the first memory device data interface and a second memory access request is processed via the second memory device data interface at substantially a same time in a parallel manner.

13. A memory module, comprising:

a memory hub device integrated into the memory module;

a first set of memory devices integrated in the memory module and coupled to the memory hub device;

a second set of memory devices integrated in the memory module and coupled to the memory hub device;

a first memory device data interface integrated in the memory hub device through which the first set of memory devices are coupled to internal logic of the memory hub device;

a second memory device data interface integrated in the memory hub device through which the second set of memory devices are coupled to internal logic of the memory hub device, wherein the first set of memory devices are separate from the second set of memory devices and the first and the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces;

a memory hub controller integrated into the memory hub device;

a link interface integrated into the memory hub device, wherein the link interface provides a communication path between an external memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface,

a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data and second set of memory devices to the link interface based on a control signal from the memory hub controller;

a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and

a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.

14. The memory module of claim 13, further comprising:

a memory hub controller integrated into the memory hub device;

a link interface integrated into the memory hub device, wherein the link interface provides a communication path between an external memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface;

a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller;

a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and

a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.

15. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises at least one memory module, and wherein the at least one memory module comprises;

a memory hub device integrated in a memory module;

a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and

a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interface, wherein the at least one memory module further comprises;

a memory hub controller integrated into the memory hub device; and

a link interface integrated into the memory hub device, wherein the link interface provides a communication oath between the memory controller and the memory hub controller and the first and second set of memory devices such that the memory hub controller receives memory access commands from the memory controller via the link interface, and wherein the memory devices receive and send data via the link interface, wherein the at least one memory module further comprises;

a first multiplexer integrated into the memory hub device, the first multiplexer being coupled to the link interface, the memory hub controller, the first memory device data interface, and the second memory device data interface, the first multiplexer being provided so as to provide read data from the first and second set of memory devices to the link interface based on a control signal from the memory hub controller,

a second multiplexer integrated into the memory hub device, the second multiplexer being coupled to the link interface, the memory hub controller, and the first memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the first set of memory devices based on a control signal from the memory hub controller; and

a third multiplexer integrated into the memory hub device, the third multiplexer being coupled to the link interface, the memory hub controller, and the second memory device data interface, the second multiplexer being provided so as to provide write data from the link interface to the second set of memory devices based on a control signal from the memory hub controller.

16. The data processing system of claim 15, wherein the memory further comprises:

a memory channel for communicating with the first set of memory devices and the second set of memory devices via the memory hub device; and

a memory controller in communication with the memory channel, wherein the memory controller generates memory access requests, receives memory access requests, and responds to memory access requests.

17. The data processing system of claim 15, wherein

memory hub controller is coupled to the first memory device data interface and the second memory device data interface.

18. The data processing system of claim 17, wherein the memory hub controller responds to access request packets from one of a memory controller external to the memory module or a downstream memory hub device of another memory module by responsively driving one or more of the first set of memory devices or the second set of memory devices using a memory device address and control bus and directing one of a read data flow selector or a write data flow selector.

19. The data processing system of claim 18, wherein the memory hub controller drives the read data flow selector to a multiplexer of the memory hub device to select outputting read data directly, from one of the first memory device data interface or the second memory device data interface, or outputting read data from a read data queue, wherein the memory hub controller drives the write data flow selector to a first multiplexer and a second multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device and wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface.

20. The data processing system of claim 17, wherein the memory hub controller, in response to a write access request packet, issues a first memory write access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory write access request to the second set of memory devices via the second memory device data interface.

21. The data processing system of claim 17, wherein the memory hub controller, in response to a read access request packet, issues a first memory read access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory read access request to the second set of memory devices via the second memory device data interface, wherein read data from the first memory read access request and the second memory read access request are directly transferred to the memory controller and wherein read data from the first memory read access request and the second memory read access request are queued prior to be transferred to the memory controller.