Capacity on demand using signaling bus control

• US 7,865,757 B2
• Filed: 01/23/2008
• Issued: 01/04/2011
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Carter, Benjamin F. III, Levesque, Stephen Roland, Borkenhagen, John Michael
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Brown; Michael J
• Application Number:
  US12/018,359
• Publication Number:
  US 20080114913A1
• Time in Patent Office: 1,077 Days
• Field of Search: 713/500, 713/501, 713/503, 370/468, 370/477
• US Class Current: 713/500
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources

Abstract

An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.

Claims

1. A computing system having a controllable capacity, comprising:

a processor;

a signaling bus coupled to the processor; and

a means for dynamically changing a percentage of dead cycles on the signaling bus;

wherein the controllable capacity of the computing system is controlled by monitoring demand on the computing system and altering the controllable capacity responsive to demand by controlling a characteristic of the signaling bus; and

wherein the characteristic of the signaling bus is bandwidth; and

wherein bandwidth is controlled using the means for dynamically changing the percentage of dead cycles on the signaling bus.

2. The computing system of claim 1, the means for dynamically changing the percentage of dead cycles on the signaling bus comprises:

a bus ready signal coupled to the processor capable of indicating that data transmitting on the signaling bus should not be used; and

a capacity on demand register capable of storing a currently authorized capacity of the computing system, the capacity on demand register coupled to the bus ready signal.

3. The computing system of claim 2, further comprising:

a shift register coupled to the capacity on demand register and to the bus ready signal, the shift register capable of being initialized by the capacity on demand register, the shift register further configured to rotate one bit position per cycle of the signaling bus.