×

Processor including efficient signature generation for logic error protection

  • US 7,865,770 B2
  • Filed: 01/10/2008
  • Issued: 01/04/2011
  • Est. Priority Date: 01/10/2008
  • Status: Active Grant
First Claim
Patent Images

1. A processor core configured to operate in a reliable execution mode, the processor core comprising:

  • an instruction decode unit configured to dispatch a same integer instruction stream to a plurality of integer execution units, and to dispatch a same floating-point instruction thread to a floating point unit;

    wherein the plurality of integer execution units is configured to operate in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction;

    wherein the floating point unit is configured to execute the same floating-point instruction thread twice;

    signature generation logic coupled to each of the plurality of integer execution units and to the floating point unit, wherein the signature generation logic is configured to generate a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each respective one of the plurality of integer execution units in response to the result signals becoming available, wherein the signature generation unit is configured to generate the signatures concurrently with execution of the integer instructions;

    wherein the signature generation logic is configured to generate a signature from result signals conveyed on result buses within the floating point unit, wherein the signature generation unit is configured to generate the signature concurrently with execution of the floating-point instructions; and

    compare logic coupled to the signature generation logic and configured to detect a mismatch between signatures from each of the plurality of integer execution units;

    wherein in response to the compare logic detecting any mismatch, the compare logic is configured to cause instructions causing the mismatch to be re-executed.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×