Decompressor/PRPG for applying pseudo-random and deterministic test patterns

• US 7,865,794 B2
• Filed: 03/12/2009
• Issued: 01/04/2011
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/402,880
• Publication Number:
  US 20090177933A1
• Time in Patent Office: 663 Days
• Field of Search: 714/724, 714/726, 714/727, 714/728, 714/729, 714/732, 714/733, 714/734, 714/738, 714/739, 714/741
• US Class Current: 714/739
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Claims

1. A method for operating a decompressor/PRPG comprising:

in a pseudo-random phase of operation;

inputting an initial value;

generating from the initial value a set of pseudo-random test patterns; and

outputting the pseudo-random test patterns;

in a deterministic phase of operation;

inputting a compressed deterministic test pattern;

decompressing the compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being input, the decompressing including logically combining one or more bits of the compressed deterministic test pattern with bits stored within the decompressor/PRPG; and

outputting the decompressed deterministic test pattern.

2. The method of claim 1 wherein the logically combining is performed with an XOR or XNOR operation.

3. The method of claim 1, further comprising applying the decompressed test pattern to scan chains of the circuit-under-test as the compressed deterministic test pattern is being input.

4. The method of claim 1 wherein inputting the compressed test pattern comprises generating a serial stream of bits representing the compressed test pattern.

5. The method of claim 1 wherein inputting the compressed test pattern comprises generating a parallel stream of bits representing the compressed test pattern.

6. The method of claim 1 wherein the compressed deterministic test pattern comprises a compressed partially specified test cube.

7. A circuit comprising:

a decompressor/PRPG;

control circuitry coupled to the decompressor/PRPG and operable to cause the decompressor/PRPG to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from a set of provided compressed deterministic patterns, the control circuitry comprising one or more logic gates that receive the compressed deterministic patterns during the deterministic phase of operation and logically combine the compressed deterministic patterns with bits stored within the decompressor/PRPG;

circuit logic; and

scan chains coupled to the circuit logic and operable to receive test patterns generated by the decompressor/PRPG and to capture responses to the test patterns generated by the circuit logic,

wherein the decompressor/PRPG is operable to decompress a compressed deterministic test pattern as the compressed deterministic test pattern is being provided to the decompressor/PRPG.

8. The circuit of claim 7, wherein the one or more logic gates are XOR or XNOR gates.

9. The circuit of claim 7 wherein the decompressor/PRPG is comprised of one or more of a linear finite state machine, a cellular automaton, or a linear feedback shift register.

10. The circuit of claim 7 wherein the decompressor/PRPG includes a phase shifter of one or more XOR or XNOR gates.

11. The circuit of claim 7 wherein the decompressor/PRPG is operable to receive from an external tester an initial value from which the decompressor/PRPG generates a set of pseudo-random test patterns.

12. The circuit of claim 7 wherein the control circuitry is operable to direct a set of compressed deterministic test patterns from an external tester to the decompressor/PRPG from which the decompressor/PRPG generates a set of decompressed deterministic test patterns.

13. The circuit of claim 7, wherein the logic gates are logic gates through which the compressed deterministic patterns pass from the external tester to the decompressor/PRPG, the logic gates being responsive to an enable signal.

14. The circuit of claim 7 wherein the decompressor/PRPG is operable to apply a decompressed deterministic test pattern to the scan chains as the compressed deterministic test pattern is being provided to the decompressor/PRPG.

15. A system, comprising:

means for inputting an initial value, generating from the initial value a set of pseudo-random test patterns, and outputting the pseudo-random test patterns; and

means for inputting a compressed deterministic test pattern, decompressing the compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being input, the decompressing including logically combining one or more bits of the compressed deterministic test pattern with stored bits, and outputting the decompressed deterministic test pattern.

16. The system of claim 15 wherein the logically combining is performed with an XOR or XNOR operation.

17. The system of claim 15, further comprising means for applying the decompressed test pattern to scan chains of the circuit-under-test as the compressed deterministic test pattern is being input.

18. The system of claim 15 wherein the compressed deterministic test pattern comprises a compressed partially specified test cube.