Fast error detection system and related methods

• US 7,865,808 B2
• Filed: 05/09/2007
• Issued: 01/04/2011
• Est. Priority Date: 05/09/2007
• Status: Active Grant

• Current Assignee: Harris Global Communications, Inc. (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Nieto, John W., Furman, William N.
• Primary Examiner(s): Chaudry; M. Mujtaba K
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US11/746,091
• Publication Number:
  US 20080279109A1
• Time in Patent Office: 1,336 Days
• Field of Search: 714/781, 714/759
• US Class Current: 714/781
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

A system apparatus and method generates a communications signal having an error detection mechanism. A circuit generates a data packet. An encoder multiplies and accumulates data words with values in a distance table containing non-repeated n-bit multipliers having “m” number of one bits that are set to obtain accumulated sum bits and appends the accumulated sum bits to the data packet as an error detection code to form a communications signal to be transmitted.

Claims

1. An apparatus for generating a communications signal having an error detection mechanism, comprising:

a circuit that generates a data packet; and

an encoder that multiplies and accumulates data words with values in a distance table array containing non-repeated n-bit values having “

m”

number of one bits set to obtain an accumulated sum and appends the sum bits to the data packet as an error detection code to form a communications signal.

2. The apparatus according to claim 1, which further comprises a digital signal processor (DSP) having a multiply/accumulate (MAC) unit for multiplying and accumulating values from the distance table with the data words.

3. The apparatus according to claim 2, wherein said DSP is operative for computing a product and adding the result to the accumulator with integers as a computed modulo of a power of two.

4. The apparatus according to claim 1, wherein said encoder is operative for multiplying the data words with values from the distance table containing pre-computed non-repeated 16-bit values.

5. The apparatus according to claim 1, wherein said encoder is operative for obtaining “

x”

number of bits as a first number of bits for the accumulated sum and reducing the sum bits down to a “

y”

number of sum bits.

6. The apparatus according to claim 1, and further comprising a parity bit added to the sum bits that are appended to the data packet.

7. The apparatus according to claim 1, wherein the values of the distance table are pre-computed and optimized to give bit errors good distance properties.

8. A system for communicating, comprising:

a transmitter, comprising,

a circuit that generates a data packet; and

an encoder that multiplies and accumulates data words with values of a distance table containing non-repeated, n-bit multipliers having “

m”

number of one bits that are set to obtain the accumulated sum bits, wherein said encoder circuit appends the sum bits to the data packet as an error detection code to form a communications signal that is transmitted; and

a receiver that receives the communications signal after it is transmitted, and comprising

a decoder circuit that processes the signal using the values of the distance table to detect errors in communication based on the accumulated sum bits appended to the data packet.

9. The system according to claim 8, wherein said transmitter and receiver each include a digital signal processor (DSP) and multiply/accumulate (MAC) unit operative for computing the accumulated sum bits.

10. A method of generating a communications signal having an error detection mechanism, comprising:

multiplying and accumulating data words with the values of a distance table containing non-repeated n-bit values having “

m”

number of one bits that are set to obtain an accumulated sum that is “

x”

bits wide; and

appending the accumulated sum bits to a data packet as an error detection code to form a communications signal.

11. The method according to claim 10, which further comprises multiplying and accumulating the data words within a multiply/accumulate (MAC) unit of a digital signal processor (DSP).

12. The method according to claim 10, which further comprises multiplying the data words with values from the distance table containing 16 bit values.

13. The method according to claim 10, which further comprises obtaining “

x”

number of bits as a first number of accumulated sum bits and reducing the sum bits down to a “

y”

number of sum bits.

14. The method according to claim 10, which further comprises replacing a bit zero of the sum bits with a parity bit.

15. The method according to claim 10, wherein the values of the distance table are pre-computed and optimized to give bit errors good distance properties.

16. The method according to claim 10, which further comprises computing a product and adding the result to an accumulator with integers as a computed modulo of a power of two.

17. The method according to claim 10, which further comprises receiving the communications signal and decoding the signal within a receiver using the values of the distance table to detect errors in communication.