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Methods of forming field effect transistors on substrates

  • US 7,867,851 B2
  • Filed: 08/30/2005
  • Issued: 01/11/2011
  • Est. Priority Date: 08/30/2005
  • Status: Expired due to Fees
First Claim
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1. A method of forming a field effect transistor on a substrate comprising trench isolation, the field effect transistor comprising a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, a transistor gate received operably proximate the channel region, and a gate dielectric layer received between the transistor gate and the channel region, each of the pair of source/drain regions having a highest dopant concentration portion which has an elevationally outermost surface and an elevationally innermost surface, the pair of source/drain regions having opposing sidewalls, the method comprising:

  • conducting a dopant activation anneal of the pair of source/drain regions;

    the opposing sidewalls of the pair of source/drain regions being formed by etching an opening into an island of semiconductive material that is completely laterally surrounded by the trench isolation, the opening being etched to be laterally centered relative to the island in at least one straight line cross section through the island, the opening also being etched into the trench isolation, the opening being etched to have a greater width within the trench isolation in a straight line cross section that is parallel the one straight line cross section through the island, the opening being etched after conducting the dopant activation anneal;

    after conducting the dopant activation anneal, forming the gate dielectric layer to be received within the opening over the opposing sidewalls of the pair of source/drain regions and over the elevationally outermost surface of the highest dopant concentration portion of each of the pair of source/drain regions;

    after forming the gate dielectric layer, depositing material from which a conductive portion of the transistor gate is made to within the opening over the gate dielectric layer, the gate dielectric layer being received over the opposing sidewalls of the pair of source/drain regions and over the elevationally outermost surface of the highest dopant concentration portion of each of the pair of source/drain regions in a finished circuitry construction incorporating the field effect transistor;

    after the depositing, etching the deposited material to have an elevationally outermost surface which is received elevationally inward of the elevationally innermost surface of the highest dopant concentration portion of each of the pair of source/drain regions;

    after etching the deposited material, forming an insulative layer over and in contact with both the etched, deposited material and the gate dielectric layer, including over and in contact with the gate dielectric layer that is over the elevationally outermost surface of the highest dopant concentration portion of each of the pair of source/drain regions;

    after forming the insulative layer, forming a contact opening at least through both the insulative layer and the gate dielectric layer for each of the pair of source/drain regions; and

    after forming the contact openings, forming conductive contacts through the contact openings to the source/drain regions.

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