Strained channel transistor formation

• US 7,867,860 B2
• Filed: 07/23/2004
• Issued: 01/11/2011
• Est. Priority Date: 07/25/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yen-Ping, Ko, Chih-Hsin, Huang, Yi-Chun
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US10/897,563
• Publication Number:
  US 20050082522A1
• Time in Patent Office: 2,363 Days
• Field of Search: 438/197, 438/303, 438/305, 438/306, 438/514, 438/530, 438/551, 438/671, 438/683, 438/700, 438/938, 438/942, 438/FOR.191, 438/285
• US Class Current: 438/285
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.

Claims

1. A method of forming a strained channel device, the method comprising:

patterning a mask on a substrate to define recess regions and a channel region;

etching back portions of the substrate defined as the recess regions;

forming a stress-inducing material in the recess regions; and

subsequently forming a gate dielectric and a gate electrode over the channel region and forming source/drain regions on opposing sides of the gate electrode, the source/drain regions being at least partially located in the stress-inducing material.

2. The method of claim 1, wherein the patterning comprises the steps of:

forming a first masking layer over an active area of the substrate;

forming a second masking layer over the first masking layer;

forming a third masking layer over the second masking layer; and

patterning the third masking layer to define the recess regions and the channel region.

3. The method of claim 2, wherein the first masking layer comprises a dielectric antireflective coating (DARC).

4. The method of claim 2, wherein the second masking layer comprises a bottom antireflective coating (BARC).

5. The method of claim 2, wherein the third masking layer comprises a photoresist.

6. The method of claim 2, wherein the third masking layer and the second masking layer are substantially removed during the etching step.

7. The method of claim 6, further comprising removing remaining portions of the first masking layer after the etching step.

8. The method of claim 1, further comprising epitaxially growing silicon over the stress-inducing material, and wherein the forming source/drain regions comprises:

performing a lightly doped drain implant and anneal, wherein the gate dielectric and the gate electrode act as a mask for the implant;

forming spacers alongside the gate dielectric and the gate electrode;

performing source/drain implant and anneal, wherein the gate dielectric, gate electrode, and spacers act as a mask; and

forming silicide in the source, drain and gate electrode.

9. A method of forming a strained channel device, the method comprising:

patterning a mask on a substrate to define recess regions and a channel region;

etching back portions of the substrate defined as the recess regions;

forming a stress-inducing material in the recess regions;

subsequently forming a gate over the channel region and source/drain regions in the stress-inducing material; and

pre-cleaning the recess regions prior to forming the stress-inducing material.

10. The method of claim 9, wherein the patterning comprises the steps of:

forming a first masking layer over an active area of the substrate;

forming a second masking layer over the first masking layer;

forming a third masking layer over the second masking layer; and

patterning the third masking layer to define the recess regions and the channel region.

11. The method of claim 10, wherein the first masking layer comprises a dielectric antireflective coating (DARC).

12. The method of claim 10, wherein the second masking layer comprises a bottom antireflective coating (BARC).

13. The method of claim 10, wherein the third masking layer comprises a photoresist.

14. The method of claim 10, wherein the third masking layer and the second masking layer are substantially removed during the etching step.

15. The method of claim 14, further comprising removing remaining portions of the first masking layer after the etching step.

16. The method of claim 9, further comprising epitaxially growing silicon over the stress-inducing material, and the forming source/drain regions comprises:

forming a gate dielectric and a gate electrode over the channel region;

performing a lightly doped drain implant and anneal, wherein the gate dielectric and the gate electrode act as a mask for the implant;

forming spacers alongside the gate dielectric and the gate electrode;

performing source/drain implant and anneal, wherein the gate dielectric, gate electrode, and spacers act as a mask; and

forming silicide in the source, drain and gate electrode.

17. A method of manufacturing a strained channel transistor comprising:

forming a source recess and a drain recess in a substrate, the source and drain recesses defining a channel region therebetween;

at least partially filling the source recess and the drain recess with a first material, the first material causing a strain upon a lattice structure of the channel region; and

subsequently forming a gate electrode over the channel region, the gate electrode having a gate dielectric layer and a conductive layer.

18. The method of claim 17, wherein the step of at least partially filling the source recess and the drain recess with a first material does not completely fill the source recess and the drain recess, and further comprising forming a cap layer over the first material in the source recess and the drain recess with a second material.

19. The method of claim 18, wherein the substrate and the second material are the same material.

20. The method of claim 18, further comprising siliciding a portion of the cap layer.

21. The method of claim 17, further comprising forming gate spacers along sidewalls of the gate electrode, the gate spacers overlying and covering a portion of the first material filling the drain recess and the source recess and leaving a portion of the first material filling the drain recess and the source recess exposed.