Liquid crystal display array board and method of fabricating the same

• US 7,868,338 B2
• Filed: 09/12/2006
• Issued: 01/11/2011
• Est. Priority Date: 11/23/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Do Young, Heo, Hae Jin
• Primary Examiner(s): Wilczewski; Mary
• Assistant Examiner(s): Thomas; Toniae M
• Application Number:
  US11/520,507
• Publication Number:
  US 20070161184A1
• Time in Patent Office: 1,582 Days
• Field of Search: 257/98, 257/309, 257/351, 257/350, 257/532, 257/E33.062, 257/E29.343, 257/E21.012, 438/29, 438/152, 438/155, 438/250, 438/393, 438/964, 438/30, 438/255, 438/398
• US Class Current: 257/98
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

A liquid crystal display array board includes a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines, a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the data wiring lines, a plurality of storage capacitor first electrodes that run parallel to the gate wiring lines and patterned to have concavo-convex patterns, a plurality of storage capacitor second electrodes integrated with the drain electrodes of the thin film transistors and formed on the storage capacitor first electrodes, and a plurality of pixel electrodes electrically connected to the drain electrodes.

Claims

1. A liquid crystal display array board comprising:

a plurality of gate wiring lines on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines;

a plurality of thin film transistors at crossings of the gate wiring lines and the data wiring lines;

a plurality of on-common storage capacitor first electrodes parallel to and spatially separated from the gate wiring lines and patterned to have concavo-convex patterns;

a plurality of electrode units, each of the electrode units having a first portion utilized as one of a plurality of on-common storage capacitor second electrodes and a second portion utilized as a corresponding one of a plurality of drain electrodes of the thin film transistors, the electrode units being on the storage capacitor first electrodes; and

a plurality of pixel electrodes spatially separated from the on-common storage capacitor second electrodes and electrically connected to the drain electrodes.

2. The liquid crystal display array board as claimed in claim 1, wherein the storage capacitor first electrodes are formed by substantially the same material as the gate wiring lines.

3. The liquid crystal display array board as claimed in claim 1, wherein the storage capacitor first electrodes are formed in substantially the same layer as the gate wiring lines.

4. The liquid crystal display array board as claimed in claim 1, wherein an insulating layer is formed between the storage capacitor first electrodes and the storage capacitor second electrodes.

5. The liquid crystal display array board as claimed in claim 4, wherein the insulating layer is a gate insulating layer.

6. The liquid crystal display array board as claimed in claim 1, wherein the thin film transistors comprise a plurality of gate electrodes, a plurality of source electrodes, the drain electrodes, and a plurality of active layers, wherein the source electrodes are connected to the data wiring lines, and wherein the gate electrodes are connected to the gate wiring lines crossing the data wiring lines to define a plurality of pixel regions.

7. A method of fabricating a liquid crystal display array board, the method comprising:

forming a plurality of gate wiring lines and a plurality of concavo-convex storage capacitor first electrodes on a substrate so that the storage capacitor first electrodes run parallel to the gate wiring lines;

forming an insulating layer on the gate wiring lines and the storage capacitor first electrodes;

forming a plurality of data wiring lines to cross the plurality of gate wiring lines; and

forming a plurality of storage capacitor second electrodes on the insulating layer so that the storage capacitor second electrodes overlap the storage capacitor first electrodes in predetermined regions,

wherein the concavo-convex patterns of the convavo-convex storage capacitor first electrodes are formed by exposing the regions in which the first storage capacitor electrodes are to be formed using a phase shift mask or a slit mask during a mask process.

8. The method as claimed in claim 7, further comprising:

forming a plurality of pixel electrodes in the pixel regions at crossings of the gate wiring lines and the data wiring lines on a protective layer.

9. The method as claimed in claim 8, wherein the pixel electrodes are electrically connected to drain electrodes of a plurality of thin film transistors through a plurality of contact holes formed in predetermined positions of the protective layer, the drain electrodes being integrated with the capacitor storage second electrodes.