Structures of and methods of fabricating trench-gated MIS devices

• US 7,868,381 B1
• Filed: 11/05/2007
• Issued: 01/11/2011
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pitzer, Domon, Bhalla, Anup, Lui, Sik, Korec, Jacek, Shi, Xiaorong
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): Diaz; Jose R
• Application Number:
  US11/982,906
• Time in Patent Office: 1,163 Days
• Field of Search: 257/331
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Claims

1. A trench-gated MIS device comprising:

a semiconductor substrate generally doped with a dopant of a first conductivity type, a trench being formed in an active region of the substrate;

an insulating layer disposed along a wall of the trench, the trench comprising a conductive gate material, a surface of the gate material being at a level below a surface of the substrate;

a nonconductive layer overlying the surface of the substrate;

a conductive layer overlying the nonconductive layer, the conductive layer comprising a current-carrying portion and a gate bus portion, the current-carrying portion and the gate bus portion being electrically isolated from each other, the nonconductive layer having a first aperture through which the current-carrying portion of the conductive layer is in electrical contact with the substrate in the active region of the device,

wherein the thickness of the nonconductive layer underlying the gate bus portion of the conductive layer is substantially the same as the thickness of the nonconductive layer underlying the current-carrying portion of the conductive layer; and

a second trench formed in the substrate, the second trench comprising conductive gate material, the nonconductive layer having a second aperture through which the current-carrying portion of the conductive layer is in electrical contact with the second trench and with an area of the substrate adjacent to the second trench to form a Schottky interface.

2. The trench-gated MIS device of claim 1 further comprising a third trench in the substrate, the third trench being located beneath the gate bus portion and comprising conductive gate material, a surface of the gate material in the third trench being at a level below the surface of the substrate, the nonconductive layer having a third aperture through which the gate bus portion of the conductive layer is in electrical contact with the gate material in the third trench.

3. The trench-gated MIS device of claim 1 wherein the conductive layer comprises metal.

4. The trench-gated MIS device of claim 3 further comprising a third trench in the substrate, the third trench being located beneath the gate bus portion and comprising conductive gate material, a surface of the gate material in the third trench being at a level below the surface of the substrate, the nonconductive layer having a third aperture through which the gate bus portion of the conductive layer is in electrical contact with the gate material in the third trench.

5. A trench-gated MIS device comprising an active device region and a channel stopper region, the device comprising:

a semiconductor substrate generally doped to a conductivity of first type;

an epitaxial layer overlying the substrate;

a first trench formed in the epitaxial layer of the active region of the device, an insulating layer disposed along a wall of the first trench, the first trench comprising a conductive gate material, a surface of the conductive gate material being at a level below a surface of the epitaxial layer;

a second trench formed in the epitaxial layer at a location between the active region and the channel stopper region, the second trench being substantially wider than the first trench in at least one location of the second trench;

a nonconductive layer overlying the epitaxial layer in the active region, the nonconductive layer having an aperture in the active region, the nonconductive layer disposed along walls of the second trench and along a bottom of the second trench;

a conductive layer overlying the nonconductive layer, the conductive layer comprising a current-carrying portion and a gate bus portion, the current-carrying portion being located in the active region, the gate bus portion being located between the active region and the channel stopper region, the current-carrying portion extending through the aperture in the nonconductive layer to make electrical contact with the epitaxial layer,

wherein the thickness of the nonconductive layer underlying the gate bus portion of the conductive layer is substantially the same as the thickness of the nonconductive layer underlying the current-carrying portion of the conductive layer.

6. The trench-gated MIS device of claim 5 further comprising a third trench in the epitaxial layer located beneath the gate bus portion, the third trench comprising conductive gate material, the nonconductive layer having a second aperture through which the gate bus portion of the conductive layer is in electrical contact with the conductive gate material in the third trench.

7. A trench-gated MIS device having an active area and a gate bus region, the device comprising:

a semiconductor substrate, a first trench being formed in the substrate in the active area and a second trench being formed in the substrate in the gate bus region, an insulating layer being disposed along a wall of each of the first and second trenches, each of the first and second trenches comprising a conductive gate material, the second trench being wider and deeper than the first trench in at least one location of the second trench, the conductive gate material in the second trench being in electrical contact with a gate bus;

at least one pair of protective trenches formed on opposite sides of the second trench, the second trench being deeper than the protective trenches, each of the protective trenches comprising conductive gate material, the conductive gate material in the protective trenches being electrically connected to the conductive gate material in the second trench.

8. The trench-gated MIS device of claim 7 wherein a mesa between at least one of the protective trenches and the second trench is allowed to electrically float.

9. The trench-gated MIS device of claim 7 wherein the protective trenches have substantially the same width and depth as the first trench.