High-voltage semiconductor device and method of fabricating the same

• US 7,868,384 B2
• Filed: 11/13/2007
• Issued: 01/11/2011
• Est. Priority Date: 11/15/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Yun, Chong-man, Kim, Chang-wook, Lee, Jae-gil, Jang, Ho-cheol
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Hall; Jessica
• Application Number:
  US11/939,264
• Publication Number:
  US 20080111207A1
• Time in Patent Office: 1,155 Days
• Field of Search: 257/341, 257/342, 257/E29.024, 257/E29.257, 257/E29.262, 257/E29.313, 257/E21.41, 257/E21.629, 257/401
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.

Claims

1. A high-voltage semiconductor device comprising:

a semiconductor layer including a top surface, a bottom surface, and a plurality of pillars of a first conductivity type defined by a plurality of trenches, wherein the trenches extend from the top surface of the semiconductor layer toward the bottom surface thereof;

a charge compensation layer of a second conductivity type disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench; and

a charge compensation plug of the first conductivity type substantially filling each groove,

wherein sidewalls of each trench are slanted.

2. The device of claim 1, wherein the charge compensation layer also extends over a bottom surface of each trench.

3. The device of claim 1, wherein the first conductivity type is N type, and the second conductivity type is P type.

4. The device of claim 1, wherein the charge compensation layer is an epitaxially grown semiconductor layer.

5. The device of claim 1, wherein the charge compensation plug is an epitaxially grown semiconductor layer.

6. The device of claim 1, wherein the sum of the amount of charges in the pillars and in the charge compensation plugs is substantially equal to the amount of charges in the charge compensation layer in a depthwise direction of the grooves.

7. The device of claim 6, wherein the pillars and the charge compensation plugs substantially have the same first dopant concentration, and the charge compensation layer has a second dopant concentration.

8. The device of claim 7, wherein the second dopant concentration is higher than the first dopant concentration.

9. The device of claim 1, wherein the trenches have a stripe shape.

10. The device of claim 1, wherein the trenches extend to the bottom surface of the semiconductor layer.

11. The device of claim 1, further comprising an impurity layer disposed under the trenches and the pillars in the semiconductor layer.

12. The device of claim 1, further comprising a plurality of wells of the second conductivity type disposed adjacent to the top surface of the semiconductor layer, wherein the wells form PN junctions with the charge compensation plugs and the pillars.

13. The device of claim 12, further comprising a plurality of source regions of a first conductivity type disposed in the wells adjacent to the top surface of the semiconductor layer.

14. The device of claim 13, further comprising a plurality of gate stacks each laterally extending over a top surface of a corresponding well and a top surface of a corresponding pillar such that an underlying region of the corresponding well forms a channel between a source region and the corresponding pillar, wherein each gate stack includes a gate insulating layer and a gate electrode layer.

15. The device of claim 1 wherein the charge compensation layer forms a PN junction with an adjacent pillar.

16. A high-voltage semiconductor device comprising:

a semiconductor layer including a top surface, a bottom surface;

a plurality of trenches in the semiconductor layer, each adjacent pair of trenches defining a mesa region therebetween;

a pillar of a first conductivity type in each mesa region between every two adjacent trenches;

a charge compensation impurity layer of a second conductivity type vertically extending in each mesa region between each pillar and an adjacent trench sidewall; and

a charge compensation plug of the first conductivity type substantially filling each trench,

wherein sidewalls of each trench are slanted.

17. The device of claim 16, wherein the sum of the amount of charges in the pillars and the charge compensation plugs is substantially equal to the amount of charges in the charge compensation impurity layer in a depthwise direction of the trenches.

18. The device of claim 17, wherein the pillars and the charge compensation plugs have substantially the same first dopant concentration, and the charge compensation impurity layer has a second dopant concentration.

19. The device of claim 18, wherein the second dopant concentration is higher than the first dopant concentration.

20. The device of claim 16, further comprising:

a plurality of wells of the second conductivity type disposed adjacent to the top surface of the semiconductor layer, wherein the wells form PN junctions with the charge compensation plugs and the pillars;

a plurality of source regions of the first conductivity type disposed in the wells adjacent to the top surface of the semiconductor layer; and

a plurality of gate stacks each laterally extending over a top surface of a corresponding well and a top surface of a corresponding pillar such that an underlying region of each corresponding well forms a channel between a source region and a corresponding pillar, wherein each gate stack includes a gate insulating layer and a gate electrode layer.

21. The device of claim 16 wherein the charge compensation layer forms a PN junction with an adjacent pillar.

22. A high-voltage semiconductor device comprising:

a semiconductor layer including a top surface, a bottom surface, and a plurality of pillars of a first conductivity type defined by a plurality of trenches, wherein the trenches extend from the top surface of the semiconductor layer toward the bottom surface thereof;

a charge compensation layer of a second conductivity type disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench; and

a charge compensation plug of the first conductivity type substantially filling each groove,

wherein the sum of the amount of charges in the pillars and in the charge compensation plugs is substantially equal to the amount of charges in the charge compensation layer in a depthwise direction of the grooves.

23. The device of claim 22, wherein the charge compensation layer also extends over a bottom surface of each trench.

24. The device of claim 22, wherein sidewalls of each trench are slanted.

25. The device of claim 22, wherein the first conductivity type is N type, and the second conductivity type is P type.

26. The device of claim 22, wherein the charge compensation layer is an epitaxially grown semiconductor layer.

27. The device of claim 22, wherein the charge compensation plug is an epitaxially grown semiconductor layer.

28. The device of claim 22, wherein the pillars and the charge compensation plugs substantially have the same first dopant concentration, and the charge compensation layer has a second dopant concentration.

29. The device of claim 28, wherein the second dopant concentration is higher than the first dopant concentration.

30. The device of claim 22, wherein the trenches have a stripe shape.

31. The device of claim 22, wherein the trenches extend to the bottom surface of the semiconductor layer.

32. The device of claim 22, further comprising an impurity layer disposed under the trenches and the pillars in the semiconductor layer.

33. The device of claim 22, further comprising a plurality of wells of the second conductivity type disposed adjacent to the top surface of the semiconductor layer, wherein the wells form PN junctions with the charge compensation plugs and the pillars.

34. The device of claim 33, further comprising a plurality of source regions of a first conductivity type disposed in the wells adjacent to the top surface of the semiconductor layer.

35. The device of claim 34, further comprising a plurality of gate stacks each laterally extending over a top surface of a corresponding well and a top surface of a corresponding pillar such that an underlying region of the corresponding well forms a channel between a source region and the corresponding pillar, wherein each gate stack includes a gate insulating layer and a gate electrode layer.

36. The device of claim 22 wherein the charge compensation layer forms a PN junction with an adjacent pillar.

37. A high-voltage semiconductor device comprising:

a semiconductor layer including a top surface, a bottom surface;

a plurality of trenches in the semiconductor layer, each adjacent pair of trenches defining a mesa region therebetween;

a pillar of a first conductivity type in each mesa region between every two adjacent trenches;

a charge compensation impurity layer of a second conductivity type vertically extending in each mesa region between each pillar and an adjacent trench sidewall; and

a charge compensation plug of the first conductivity type substantially filling each trench,

wherein the sum of the amount of charges in the pillars and the charge compensation plugs is substantially equal to the amount of charges in the charge compensation impurity layer in a depthwise direction of the trenches.

38. The device of claim 37, wherein sidewalls of each trench are slanted.

39. The device of claim 37, wherein the pillars and the charge compensation plugs have substantially the same first dopant concentration, and the charge compensation impurity layer has a second dopant concentration.

40. The device of claim 39, wherein the second dopant concentration is higher than the first dopant concentration.

41. The device of claim 37, further comprising:

a plurality of wells of the second conductivity type disposed adjacent to the top surface of the semiconductor layer, wherein the wells form PN junctions with the charge compensation plugs and the pillars;

a plurality of source regions of the first conductivity type disposed in the wells adjacent to the top surface of the semiconductor layer; and

a plurality of gate stacks each laterally extending over a top surface of a corresponding well and a top surface of a corresponding pillar such that an underlying region of each corresponding well forms a channel between a source region and a corresponding pillar, wherein each gate stack includes a gate insulating layer and a gate electrode layer.

42. The device of claim 37 wherein the charge compensation layer forms a PN junction with an adjacent pillar.