Semiconductor device

• US 7,868,416 B2
• Filed: 05/04/2010
• Issued: 01/11/2011
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fukuzumi, Yoshiaki, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu, Matsuoka, Yasuyuki
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US12/773,038
• Publication Number:
  US 20100219465A1
• Time in Patent Office: 252 Days
• Field of Search: 438/221, 438/319, 438/411, 438/619, 257520-522, 257/E23.013, 257/E21.573
• US Class Current: 257/522
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.

Claims

1. A semiconductor device comprising:

a substrate;

a source region formed on the surface portion of the substrate,

a first insulating layer formed on the substrate;

a gate electrode formed on the first insulating layer;

a second insulating layer formed on the gate electrode;

a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing an insulating region;

a gate insulating film surrounding the body section, and formed between the body section and the gate electrode; and

a drain region connected with the body section;

wherein the gate electrode has a boron-doped first amorphous silicon film, a second amorphous silicon film formed on the first amorphous silicon film, and a boron-doped third amorphous silicon film formed on the second amorphous silicon film; and

the diameter of the body section on the second amorphous silicon film portion is larger than the diameter on the first amorphous silicon film portion and the diameter on the third amorphous silicon film portion.

2. The semiconductor device according to claim 1, wherein the insulating region is a void.

3. The semiconductor device according to claim 1, wherein the insulating region is an insulating film.

4. The semiconductor device according to claim 1, wherein the diameter of the body section on at least a part of the gate electrode is larger than the diameter on the first insulating layer portion and the diameter on the second insulating layer portion.

5. The semiconductor device according to claim 1, wherein the first insulating layer has a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film sequentially laminated;

the second insulating layer has a third silicon oxide film, a second silicon nitride film, and a fourth silicon oxide film sequentially laminated; and

the diameter of the body section on the second silicon oxide film portion, the diameter on the third silicon oxide film portion, and the diameter on the fourth silicon oxide film portion are larger than the diameter on the first silicon nitride film portion and the diameter on the second silicon nitride film portion.

6. The semiconductor device according to claim 1, wherein the gate insulating film is an ONO film formed on an oxide film, a nitride film, and an oxide film.

7. The semiconductor device according to claim 1, further comprising:

an insulating film surrounding the source region; and

a gate electrode formed on the second insulating layer and a third insulating layer formed on the gate electrode;

wherein

the gate insulating film has a charge accumulating ability.

8. The semiconductor device according to claim 1, wherein the source region is replaced by the drain region and the drain region is replaced by the source region.