Low stress cavity package

• US 7,868,433 B2
• Filed: 08/29/2008
• Issued: 01/11/2011
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Yeong, Shee Min, Lim, Peng Soon, How, You Chye
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US12/202,112
• Publication Number:
  US 20100052123A1
• Time in Patent Office: 865 Days
• Field of Search: 438/123, 257/676, 257/E21.51, 257/E23.037
• US Class Current: 257/676
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83951 Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

Claims

1. A method for packaging integrated circuit devices, comprising:

providing a leadframe having a number of leads suitable for use in packaging an integrated circuit die, each lead having a first surface arranged for connection with an associated bond pad on an active surface of the die and a second surface opposite the first surface, the second surfaces of the leads being adhesively secured to an adhesive film;

reflowing solder between the first surfaces of selected leads and selected bond pads on the active surface of the die to form solder joint connections that physically and electrically connect the die with the leadframe;

dispensing a viscous thermosetting material substantially around the periphery of the active surface of the die such that the viscous thermosetting material substantially fills any gaps between the solder joint connections between the active surface of the die and the adhesive film, wherein the viscous thermosetting material, the solder joint connections, the active surface of the die and the adhesive film define a cavity between the active surface of the die and the adhesive film that isolates selected regions of the active surface of the die from stresses; and

encapsulating at least portions of the die, leads, solder joint connections and the adhesive film with a molding material, wherein the viscous thermosetting material, the active surface of the die and the adhesive film substantially prevent molding material from entering the cavity.

2. The method of claim 1, wherein the thickness of the adhesive film ranges between approximately 50 to 100 microns.

3. The method of claim 1, wherein the adhesive film is adapted to tolerate temperatures of at least approximately 250°

C. without losing a substantial degree of adhesiveness.

4. The method of claim 1, wherein the viscosity of the thermosetting material is in the range of approximately 86 pascal-seconds to 90 pascal-seconds.

5. The method of claim 1, wherein the die includes a back surface opposite the active surface, the method further comprising selectively solder plating portions of the back surface of the die and the leadframe to facilitate electrical connections with external devices.

6. The method of claim 1, wherein the encapsulating of at least portions of the die, leads, solder joint connections and the adhesive film includes encapsulating a portion of the integrated circuit die without covering a back surface opposite the active surface of the die such that the back surface of the die is exposed to facilitate heat dissipation.

7. The method of claim 1, wherein the dispensing of the viscous thermosetting material is performed under a temperature at a first elevated level, such that the pressure inside the cavity, after the temperature cools to a second level substantially lower than the first level, is significantly lower than the ambient pressure outside the cavity.

8. An integrated circuit package, comprising:

an integrated circuit die having an active surface and a back surface opposite the active surface, the active surface including a sensitive region;

a plurality of leads, each lead having a first surface and a second surface opposite the first surface;

a plurality of solder joint connections that mechanically and electrically connect the first surfaces of selected leads with associated bond pads on the active surface of the die;

an adhesive film adhesively secured to second surfaces of the leads;

a viscous thermosetting material that substantially fills any gaps between the solder joint connections between the active surface of the die and the adhesive film, wherein the viscous thermosetting material, the solder joint connections, the active surface of the die and the adhesive film define a cavity between the active surface of the die and the adhesive film that isolates the sensitive region on the active surface of the die from stresses; and

a molding material that encapsulates at least portions of the die, leads, solder joint connections and the adhesive film with a molding material, wherein the viscous thermosetting material, the active surface of the die and the adhesive film substantially prevent molding material from entering the cavity.

9. The integrated circuit package of claim 8, wherein the thickness of the adhesive film ranges between approximately 50 to 100 microns.

10. The integrated circuit package of claim 8, wherein the adhesive film is adapted to tolerate temperatures of at least approximately 250°

C. without losing a substantial degree of adhesiveness.

11. The integrated circuit package of claim 8, wherein the viscosity of the thermosetting material is in the range of approximately 86 pascal-seconds to 90 pascal-seconds.

12. The integrated circuit package of claim 8, wherein portions of the non-active surface of the die and the leadframe are solder plated to facilitate electrical connections between the die and external devices.

13. The integrated circuit package of claim 8, wherein the molding material encapsulates the integrated circuit die without covering at least a portion of the non-active surface of the die, such that heat dissipation through the non-active surface of the die is facilitated.

14. The integrated circuit package of claim 8, wherein the pressure within the cavity is substantially less than the ambient pressure immediately outside the molding material.