Layered chip package and method of manufacturing same

• US 7,868,442 B2
• Filed: 06/30/2008
• Issued: 01/11/2011
• Est. Priority Date: 06/30/2008
• Status: Expired due to Fees

• Current Assignee: Headway Technologies Incorporated, TDK Corporation
• Original Assignee: Headway Technologies Incorporated, TDK Corporation
• Inventors: Sueki, Satoru, Okuzawa, Nobuyuki, Ito, Hiroyuki, Harada, Tatsuya, Sasaki, Yoshitaka
• Primary Examiner(s): SMITH, MATTHEW S
• Application Number:
  US12/216,143
• Publication Number:
  US 20090321956A1
• Time in Patent Office: 925 Days
• Field of Search: 257/686, 257/777, 257/723, 257/724
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 Specific sequence of method steps
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces.

Claims

1. A layered chip package comprising:

a main body having a top surface, a bottom surface and four side surfaces; and

wiring disposed on at least one of the side surfaces of the main body, wherein;

the main body includes a plurality of layer portions stacked;

each of the plurality of layer portions includes;

a semiconductor chip having a first surface with a device formed thereon, a second surface opposite to the first surface, and four side surfaces;

an insulating portion covering at least one of the four side surfaces of the semiconductor chip; and

a plurality of electrodes connected to the semiconductor chip;

the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;

each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed;

the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions; and

the plurality of layer portions include at least a pair of layer portions that are disposed such that the first surfaces of the respective semiconductor chips face toward each other.

2. The layered chip package according to claim 1, wherein:

the pair of layer portions comprises a first layer portion including a first semiconductor chip and a second layer portion including a second semiconductor chip;

the first semiconductor chip includes a plurality of first terminals aligned in a predetermined order;

the second semiconductor chip includes a plurality of second terminals aligned in a predetermined order in correspondence with the first terminals;

the first layer portion includes, as the plurality of electrodes, a plurality of first electrodes connected to the plurality of first terminals;

the second layer portion includes, as the plurality of electrodes, a plurality of second electrodes connected to the plurality of second terminals; and

as seen in one direction under a condition in which the first and second layer portions are disposed such that the respective first surfaces of the first and second semiconductor chips face toward each other, the order in which the second terminals are aligned is the reverse of the order in which the first terminals are aligned, the end faces of the first electrodes located at the at least one of the side surfaces of the main body are aligned in an order that is the same as the order in which the corresponding first terminals are aligned, and the end faces of the second electrodes located at the at least one of the side surfaces of the main body are aligned in an order that is the reverse of the order in which the corresponding second terminals are aligned.