SRAM based one-time-programmable memory

• US 7,869,251 B2
• Filed: 09/26/2008
• Issued: 01/11/2011
• Est. Priority Date: 09/26/2008
• Status: Expired due to Fees

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Ramesh, Subramanian, Castagnetti, Ruggero, Venkatraman, Ramnath
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): King; Douglas
• Application Number:
  US12/239,469
• Publication Number:
  US 20100080035A1
• Time in Patent Office: 837 Days
• Field of Search: 365/94, 365/96, 365/104, 365/154
• US Class Current: 365/104
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.

Claims

1. A method of providing high-speed One-Time-Programmable (OTP) memory comprising:

providing a Static Random Access Memory (SRAM) cell circuit using Metal-Oxide Semiconductor (MOS) type transistors said SRAM cell circuit having a first electrical node SN and a second electrical node SNB, said MOS type transistors having two predetermined voltage ranges corresponding to data values of LOW and HIGH in accordance with characteristics of MOS transistor technology used to create said MOS type transistors, said first electrical node SN having a node SN voltage value corresponding to a SN data value, said second electrical node SNB having a node SNB voltage value corresponding to a SNB data value, and said SNB data value being a complementary data value of said SN data value;

providing a Vdd voltage corresponding to a HIGH target voltage for said HIGH data value;

providing a Vss voltage corresponding to a LOW target voltage for said LOW data value;

providing a plurality of damageable MOS type transistors that have equivalent voltage ranges for said LOW and HIGH data values as said SRAM cell circuit MOS type transistors, said plurality of damageable MOS type transistors having gates, drains, and sources, said damageable MOS transistors further having characteristic parasitic bipolar junction transistors present within said damageable MOS transistors that causes said damageable MOS transistors to break down and short out when a burn-in voltage that approaches a trigger voltage V_TR of said damageable MOS transistors is applied across said drains and said sources of said damageable MOS transistors when said damageable MOS transistors are in an ON STATE but not when said damageable MOS transistors are in an OFF STATE, said trigger voltage V_TR of said damageable MOS transistor being a voltage matching a position on a characteristic current to voltage curve of said damageable MOS technology characteristics where a snapback characteristic of said characteristic parasitic bipolar junction transistors appears on said characteristic current to voltage curve when said damageable MOS transistors are in said ON STATE, said ON STATE and said OFF STATE of said damageable transistors being controlled by a gate voltage applied to said gates of said damageable MOS transistors in accordance with damageable MOS technology characteristics of said damageable MOS type transistors, when said damageable MOS transistors are in said ON STATE current flow between said drains and said sources of said damageable MOS transistors is permitted, when said damageable MOS transistors are in said OFF STATE current flow between said drains and said sources of said damageable MOS transistor is substantively not permitted;

providing a programming circuit that has a first group of MOS transistors and a second group of MOS transistors, said first group of MOS transistors and said second group of MOS transistors being comprised of subsets of said plurality of damageable MOS type transistors, said first group of MOS transistors comprising at least one damageable MOS transistor, said gates of said first group of MOS transistors being connected to said first electrical node SN of said SRAM cell, said drains and said sources of said first group of MOS transistors being connected in series between a programming Power Line PL and a third electrical node C, said second group of MOS transistors comprising at least one damageable MOS type transistor, said gates of said second group of MOS transistors being connected to said second electrical node SNB of said SRAM cell, said drains and said sources of said second group of MOS transistors being connected in series between said programming Power Line PL and said third electrical node C;

combining said SRAM cell circuit and said programming circuit as an OTP cell circuit;

powering said OTP cell circuit such that said SRAM cell circuit is operational and said programming Power Line PL and said third electrical node C are at a normal operation equivalent voltage level;

storing a desired data value in said SRAM cell circuit such that said electrical node SN is at said desired data value and said electrical node SNB is at said complementary data value of said desired data value;

programming said programming circuit to a programmed state by connecting said third electrical Node C to said Vdd voltage and by applying a programming voltage to said programming Power Line PL, said programming voltage being a voltage that causes said voltage differential between said programming Power Line PL and said third electrical node C to substantively be said burn-in voltage, thereby causing whichever of said first group of MOS transistors and said second group of MOS transistors is in said ON STATE to break down and short out, which of said first group of MOS transistors and said second group of MOS transistors is in said ON STATE being determined by said SN data value connected to said gates of said first group of MOS transistors and said SNB data value that is said complementary data value of said SN data value connected to said gates of said second group of MOS transistors of said SRAM cell circuit; and

setting said programming Power Line PL and said third electrical node C to said normal operation equivalent voltage level applied prior to said programming such that whichever of said first group of MOS transistors connected to electrical node SN of said SRAM cell circuit and said second group of MOS transistors connected to said electrical node SNB of said SRAM cell circuit was broken down and shorted out during programming to electrically connect said respective electrical node SN or said electrical node SNB of said SRAM cell circuit to said normal operation equivalent voltage level of said electrical node C and said programming Power Line PL, thereby forcing said respective electrical node SN or electrical node SNB to correspond to said HIGH or LOW data value corresponding to said normal operation equivalent voltage level of said electrical node C and said programming Power Line PL regardless of attempts to write a different data value to said SRAM cell circuit.

2. The method of claim 1 further comprising:

providing a plurality of said OTP cell circuits to create an OTP memory array such that said OTP memory array provides a desired amount of OTP memory storage; and

,

connecting each programming circuit of said OTP memory array to a common programming Power Line PL and a common third electrical node C such that said plurality of said OTP cell circuits are programmed concurrently by said programming voltage applied to said programming Power Line PL.

3. The method of claim 2 further comprising:

providing a plurality of said OTP memory arrays such that each OTP memory array of said plurality of memory arrays has a separate common programming Power Line PL such that each OTP memory array of said plurality of memory arrays may be programmed independently of other memory arrays in said plurality of memory arrays;

programming a first subset group of OTP memory arrays of said plurality of OTP memory arrays to permanently store a desired data set; and

,

operating a second subset group of OTP memory arrays of said plurality of memory arrays as standard SRAM volatile memory.

4. The method of claim 1 wherein said programming process further comprises:

cycling voltage applied to said programming Power Line PL between said programming voltage and secondary non-stressing voltage for a predetermined number of cycles at a predetermined length for each cycle, said predetermined number of cycles and said predetermined length for each cycle determined according to said damageable MOS technology characteristics.

5. The method of claim 4:

wherein said secondary non-stressing voltage is one of the group comprising;

said Vdd voltage, said Vss voltage, electrical ground, and zero volts; and

,

wherein said normal operation equivalent voltage is one of the group comprising;

said Vdd voltage, said Vss voltage, and electrical ground.

6. The method of claim 4 wherein said burn-in voltage that approaches said trigger voltage V_TR of said damageable MOS transistors is substantively within one volt of reaching said trigger voltage V_TR.

7. The method of claim 1:

wherein said damageable MOS transistors used in said programming circuit are folded-gate devices;

wherein said SRAM cell circuit is placed on a separate piece of diffusion from said programming circuit; and

,

wherein channel types of said damageable MOS transistors used in said programming circuit are one of the group comprising;

p-channel (PMOS) and n-channel (NMOS).

8. The method of claim 1 further comprising:

powering down said OTP cell circuit; and

,

powering said SRAM cell circuit by ramping up a power supply at a controlled slower rate than that for said programming circuit such that said SRAM cell circuit is powered up after said programming circuit and said SRAM cell circuit returned to said programmed state on OTP cell circuit start-up.

9. The method of claim 1 wherein said SRAM cell circuit is a volatile memory cell circuit based on a non-SRAM circuit structure that has electrical nodes that substantively correspond to said electrical node SN at said SN data value and said electrical node SNB at said complementary data value of said SN data value and are connected to said programming circuit as are said electrical node SN and said electrical node SNB.

10. A One-Time-Programmable (OTP) memory device comprising:

a Static Random Access Memory (SRAM) cell circuit using Metal-Oxide Semiconductor (MOS) type transistors said SRAM cell circuit having a first electrical node SN and a second electrical node SNB, said MOS type transistors having two predetermined voltage ranges corresponding to data values of LOW and HIGH in accordance with characteristics of MOS transistor technology used to create said MOS type transistors, said first electrical node SN having a node SN voltage value corresponding to a SN data value, said second electrical node SNB having a node SNB voltage value corresponding to a SNB data value, and said SNB data value being a complementary data value of said SN data value;

a Vdd voltage corresponding to a HIGH target voltage for said HIGH data value;

a Vss voltage corresponding to a LOW target voltage for said LOW data value;

a plurality of damageable MOS type transistors that have equivalent voltage ranges for said LOW and HIGH data values as said SRAM cell circuit MOS type transistors, said plurality of damageable MOS type transistors having gates, drains, and sources, said damageable MOS transistors further having characteristic parasitic bipolar junction transistors present within said damageable MOS transistors that causes said damageable MOS transistors to break down and short out when a burn-in voltage that approaches a trigger voltage V_TR of said damageable MOS transistors is applied across said drains and said sources of said damageable MOS transistors when said damageable MOS transistors are in an ON STATE but not when said damageable MOS transistors are in an OFF STATE, said trigger voltage V_TR of said damageable MOS transistors being a voltage matching a position on a characteristic current to voltage curve of said damageable MOS technology characteristics where a snapback characteristic of said characteristic parasitic bipolar junction transistors appears on said characteristic current to voltage curve when said damageable MOS transistors are in said ON STATE, said ON STATE and said OFF STATE of said damageable transistors being controlled by a gate voltage applied to said gates of said damageable MOS transistors in accordance with damageable MOS technology characteristics of said damageable MOS type transistors, when said damageable MOS transistors are in said ON STATE current flow between said drains and said sources of said damageable MOS transistors is permitted, when said damageable MOS transistors are in said OFF STATE current flow between said drains and said sources of said damageable MOS transistors is substantively not permitted;

a programming circuit that has a first group of MOS transistors and a second group of MOS transistors, said first group of MOS transistors and said second group of MOS transistors being comprised of subsets of said plurality of damageable MOS type transistors, said first group of MOS transistors comprising at least one damageable MOS transistor, said gates of said first group of MOS transistors being connected to said first electrical node SN of said SRAM cell, said drains and said sources of said first group of MOS transistors being connected in series between a programming Power Line PL and a third electrical node C, said second group of MOS transistors comprising at least one damageable MOS type transistor, said gates of said second group of MOS transistors being connected to said second electrical node SNB of said SRAM cell, said drains and said sources of said second group of MOS transistors being connected in series between said programming Power Line PL and said third electrical node C;

an OTP cell circuit that is a combination of said SRAM cell circuit and said programming circuit; and

,

a programming system for said OTP cell circuit that;

powers said OTP cell circuit such that said SRAM cell circuit is operational and said programming Power Line PL and said third electrical node C are at a normal operation equivalent voltage level;

stores a desired data value in said SRAM cell circuit such that said electrical node SN is at said desired data value and said electrical node SNB is at said complementary data value of said desired data value;

programs said programming circuit to a programmed state by connecting said third electrical Node C to said Vdd voltage and by applying a programming voltage to said programming Power Line PL, said programming voltage being a voltage that causes said voltage differential between said programming Power Line PL and said third electrical node C to substantively be said burn-in voltage, thereby causing whichever of said first group of MOS transistors and said second group of MOS transistors is in said ON STATE to break down and short out, which of said first group of MOS transistors and said second group of MOS transistors is in said ON STATE being determined by said SN data value connected to said gates of said first group of MOS transistors and said SNB data value that is said complementary data value of said SN data value connected to said gates of said second group of MOS transistors of said SRAM cell circuit; and

,

sets said programming Power Line PL and said third electrical node C to said normal operation equivalent voltage level applied prior to said programming such that whichever of said first group of MOS transistors connected to electrical node SN of said SRAM cell circuit and said second group of MOS transistors connected to said electrical node SNB of said SRAM cell circuit was broken down and shorted out during programming to electrically connect said respective electrical node SN or said electrical node SNB of said SRAM cell circuit to said normal operation equivalent voltage level of said electrical node C and said programming Power Line PL, thereby forcing said respective electrical node SN or electrical node SNB to correspond to said HIGH or LOW data value corresponding to said normal operation equivalent voltage level of said electrical node C and said programming Power Line PL regardless of attempts to write a different data value to said SRAM cell circuit.

11. The one-time-programmable (OTP) memory device of claim 10 further comprising:

a plurality of said OTP cell circuits that create an OTP memory array such that said OTP memory array provides a desired amount of OTP memory storage, each programming circuit of said OTP memory array connected to a common programming Power Line PL and a common third electrical node C such that said plurality of said OTP cell circuits are programmed concurrently by said programming voltage applied to said programming Power Line PL.

12. The one-time-programmable (OTP) memory device of claim 11 further comprising:

a plurality of said OTP memory arrays, each OTP memory array of said plurality of memory arrays having a separate common programming Power Line PL such that each OTP memory array of said plurality of memory arrays may be programmed independently of other memory arrays in said plurality of memory arrays;

a first subset group of OTP memory arrays of said plurality of OTP memory arrays programmed to permanently store a desired data set; and

,

a second subset group of OTP memory arrays of said plurality of memory arrays that operate as standard SRAM volatile memory.

13. The one-time-programmable (OTP) memory device of claim 10 wherein said programming system further comprises:

cycling voltage applied to said programming Power Line PL between said programming voltage and a secondary non-stressing voltage for a predetermined number of cycles at a predetermined length for each cycle, said predetermined number of cycles and said predetermined length for each cycle determined according to said damageable MOS technology characteristics.

14. The one-time-programmable (OTP) memory device of claim 13:

wherein said secondary non-stressing voltage is one of the group comprising;

said Vdd voltage, said Vss voltage, electrical ground, and zero volts; and

,

wherein said normal operation equivalent voltage is one of the group comprising;

said Vdd voltage, said Vss voltage, and electrical ground.

15. The one-time-programmable (OTP) memory device of claim 13 wherein said burn-in voltage that approaches said trigger voltage V_TR of said damageable MOS transistors is substantively within one volt of reaching said trigger voltage V_TR.

16. The one-time-programmable (OTP) memory device of claim 10:

wherein said damageable MOS transistors used in said programming circuit are folded-gate devices;

wherein said SRAM cell circuit is placed on a separate piece of diffusion from said programming circuit; and

,

wherein channel types of said damageable MOS transistors used in said programming circuit are one of the group comprising;

p-channel (PMOS) and n-channel (NMOS).

17. The one-time-programmable (OTP) memory device of claim 10 further comprising a cell power supply that powers up said SRAM cell circuit by ramping up at a controlled slower rate than that for said programming circuit such that said SRAM cell circuit is powered up after said programming circuit and said SRAM cell circuit is returned to said programmed state on OTP cell circuit start-up.

18. The one-time-programmable (OTP) memory device of claim 10 wherein said SRAM cell circuit is a volatile memory cell circuit based on a non-SRAM circuit structure that has electrical nodes that substantively correspond to said electrical node SN at said SN data value and said electrical node SNB at said complementary data value of said SN data value and are connected to said programming circuit as are said electrical node SN and said electrical node SNB.