Reducing the impact of interference during programming

• US 7,869,273 B2
• Filed: 09/04/2007
• Issued: 01/11/2011
• Est. Priority Date: 09/04/2007
• Status: Expired

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Yero, Emilio, Lee, Dana
• Primary Examiner(s): Yoha; Connie C
• Application Number:
  US11/849,992
• Publication Number:
  US 20090059660A1
• Time in Patent Office: 1,225 Days
• Field of Search: 365/185.02, 365/185.22, 365/185.23, 365/230.04
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

Claims

1. A method for programming non-volatile storage, comprising:

performing programming on a first group of non-volatile storage elements at a first time;

performing programming on a second group of non-volatile storage elements at a second time different from said first time;

said performing programming on said first group of non-volatile storage elements at said first time and said performing programming on said second group of non-volatile storage elements at said second time are performed after and in response to a first trigger; and

said method further comprises performing one or more program cycles prior to said first trigger, each of said one or more program cycles includes programming said first group of non-volatile storage elements and said second group of non-volatile storage elements together.

2. A method according to claim 1, wherein:

said first group of non-volatile storage elements are connected to a first control line; and

said second group of non-volatile storage elements are connected to said first control line.

3. A method according to claim 1, wherein:

said first group of non-volatile storage elements are connected to a word line;

said second group of non-volatile storage elements are connected to said word line; and

each non-volatile storage element of said first group of non-volatile storage elements and said second group of non-volatile storage elements are connected to different bit lines in an interleaving manner.

4. A method according to claim 1, wherein:

said performing programming on said first group of non-volatile storage elements includes applying a first program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements, inhibiting said second group of non-volatile storage elements from programming in response to said first program pulse, and allowing said first group of non-volatile storage elements to program in response to said first program pulse; and

said performing programming on said second group of non-volatile storage elements includes applying a second program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements, inhibiting said first group of non-volatile storage elements from programming in response to said second program pulse, and allowing said second group of non-volatile storage elements to program in response to said second program pulse.

5. A method according to claim 4, wherein:

each non-volatile storage element of said first group of non-volatile storage elements and said second group of non-volatile storage elements are connected to different control lines;

said control lines include even control lines and odd control lines; and

said first group of non-volatile storage elements are connected to said even control lines; and

said second group of non-volatile storage elements are connected to said odd control lines.

6. A method according to claim 5, wherein:

said first group of non-volatile storage elements is arranged in an interleaving manner with said second group of non-volatile storage elements.

7. A method according to claim 1, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements do not have any non-volatile storage elements in common.

21. A method according to claim 1, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements are flash memory devices.

22. A method according to claim 1, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements are NAND flash memory devices.

8. A method for programming non-volatile storage, comprising:

performing programming on a first group of non-volatile storage elements at a first time

performing programming on a second group of non-volatile storage elements at a second time different from said first time

verifying said first group of non-volatile storage elements and said second group of non-volatile storage elements together;

said performing programming on said first group of non-volatile storage elements at said first time and said performing programming on said second group of non-volatile storage elements at said second time are performed after and in response to a first trigger; and

said method further comprises performing one or more program cycles prior to said first trigger, each of said one or more program cycles includes programming said first group of non-volatile storage elements and said second group of non-volatile storage elements together.

9. A method according to claim 8, wherein:

said first trigger includes a programming pulse magnitude reaching a trigger voltage.

10. A method according to claim 9, further comprising:

determining said trigger voltage for said first group of non-volatile storage elements and said second group of non-volatile storage elements subsequent to manufacture of said first group of non-volatile storage elements and said second group of non-volatile storage elements.

11. A method according to claim 8, wherein:

said performing programming on said first group of non-volatile storage elements at said first time and said performing programming on said second group of non-volatile storage elements at said second time are performed prior to a second trigger; and

said method further comprises performing one or more additional cycles subsequent to said second trigger, each of said one or more additional cycles includes programming said first group of non-volatile storage elements and said second group of non-volatile storage elements together.

12. A method according to claim 8, wherein:

said first group of non-volatile storage elements are connected to a first word line;

said second group of non-volatile storage elements are connected to said word line; and

each non-volatile storage element of said first group of non-volatile storage elements and said second group of non-volatile storage elements are connected to different bit lines in an interleaving manner.

13. A method according to claim 12, further comprising:

said performing programming on said first group of non-volatile storage elements includes applying a first program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements, inhibiting said second group of non-volatile storage elements from programming in response to said first program pulse, and allowing said first group of non-volatile storage elements to program in response to said first program pulse; and

said performing programming on said second group of non-volatile storage elements includes applying a second program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements, inhibiting said first group of non-volatile storage elements from programming in response to said second program pulse, and allowing said second group of non-volatile storage elements to program in response to said second program pulse.

14. A method according to claim 8, further comprising:

dynamically adjusting said first trigger during operation of said first group of non-volatile storage elements and said second group of non-volatile storage elements.

15. A method according to claim 8, further comprising:

adjusting said first trigger based on program-erase cycles.

16. A method according to claim 8, further comprising:

adjusting said first trigger based on temperature.

17. A method for programming non-volatile storage, comprising:

performing programming on a first group of non-volatile storage elements at a first time;

performing programming on a second group of non-volatile storage elements at a second time different from said first time;

verifying said first group of non-volatile storage elements and said second group of non-volatile storage elements together;

said performing programming on said first group of non-volatile storage elements at said first time and said performing programming on said second group of non-volatile storage elements at said second time are performed prior to and until a condition is detected; and

said method further comprises performing one or more additional cycles subsequent to said condition being detected, each of said one or more additional cycles includes programming said first group of non-volatile storage elements and said second group of non-volatile storage elements together.

18. A method according to claim 17, further comprising:

determining how many of said first group of non-volatile storage elements and said second group of non-volatile storage elements are still being programmed and have a neighbor that is selected for programming; and

detecting said condition based on how many of said first group of non-volatile storage elements and said second group of non-volatile storage elements are still being programmed and have a neighbor that is selected for programming.

19. A method according to claim 17, further comprising:

determining how many of said first group of non-volatile storage elements and said second group of non-volatile storage elements are still being programmed and have a neighbor that is selected for programming using extrapolation; and

detecting said condition based on how many of said first group of non-volatile storage elements and said second group of non-volatile storage elements are still being programmed and have a neighbor that is selected for programming.

20. A method according to claim 17, further comprising:

determining how many of said first group of non-volatile storage elements and said second group of non-volatile storage elements are still being programmed; and

detecting said condition based on how many of said first group of non-volatile storage elements and said second group of non-volatile storage elements are still being programmed.

23. A non-volatile storage apparatus, comprising:

a plurality of non-volatile storage elements including a first group of non-volatile storage elements and a second group of non-volatile storage elements; and

one or more managing circuits in communication with said non-volatile storage elements, said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements after and in response to a first trigger, said one or more managing circuits program said first group of non-volatile storage elements together with said second group of non-volatile storage elements prior to said first trigger.

24. A non-volatile storage apparatus according to claim 23, further comprising:

a control line, said first group of non-volatile storage elements are connected to said control line and said second group of non-volatile storage elements are connected to said control line.

25. A non-volatile storage apparatus according to claim 23, further comprising:

a word line, said first group of non-volatile storage elements are connected to said word line and said second group of non-volatile storage elements are connected to said word line; and

bit lines, each non-volatile storage element of said first group of non-volatile storage elements and said second group of non-volatile storage elements are connected to different bit lines in an interleaving manner.

26. A non-volatile storage apparatus according to claim 23, wherein:

said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements by applying a first program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements while inhibiting said second group of non-volatile storage elements from programming and applying a second program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements while inhibiting said first group of non-volatile storage elements from programming.

27. A non-volatile storage apparatus according to claim 23, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements do not have any non-volatile storage elements in common.

28. A non-volatile storage apparatus according to claim 23, further comprising:

control lines, each non-volatile storage element of said first group of non-volatile storage elements and said second group of non-volatile storage elements are connected to different control lines, said control lines include even control lines and odd control lines, said first group of non-volatile storage elements are connected to said even control lines, said second group of non-volatile storage elements are connected to said odd control lines.

29. A non-volatile storage apparatus according to claim 23, wherein:

said first group of non-volatile storage elements is arranged in an interleaving manner with respect to said second group of non-volatile storage elements.

39. A non-volatile storage apparatus according to claim 23, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements are flash memory devices.

40. A non-volatile storage apparatus according to claim 23, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements are NAND flash memory devices.

30. A non-volatile storage apparatus, comprising:

a plurality of non-volatile storage elements including a first group of non-volatile storage elements and a second group of non-volatile storage elements; and

one or more managing circuits in communication with said non-volatile storage elements, said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements, said one or more managing circuits verify said first group of non-volatile storage elements together with verifying said second group of non-volatile storage elements, said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements after and in response to a first trigger, said one or more managing circuits program said first group of non-volatile storage elements together with said second group of non-volatile storage elements prior to said first trigger.

31. A non-volatile storage apparatus according to claim 30, wherein:

said first trigger includes a voltage level for a program pulse concurrently applied to said first group of non-volatile storage elements and said second group of non-volatile storage elements.

32. A non-volatile storage apparatus according to claim 30, wherein:

said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements prior to a second trigger; and

said one or more managing circuits program said first group of non-volatile storage elements together with said second group of non-volatile storage elements together subsequent to and in response to said second trigger.

33. A non-volatile storage apparatus according to claim 30, further comprising:

a word line, said first group of non-volatile storage elements are connected to said word line and said second group of non-volatile storage elements are connected to said word line; and

bit lines, each non-volatile storage element of said first group of non-volatile storage elements and said second group of non-volatile storage elements are connected to different bit lines.

34. A non-volatile storage apparatus according to claim 33, wherein:

said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements by applying a first program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements while inhibiting said second group of non-volatile storage elements from programming and applying a second program pulse to said first group of non-volatile storage elements and said second group of non-volatile storage elements while inhibiting said first group of non-volatile storage elements from programming.

35. A non-volatile storage apparatus according to claim 30, wherein:

said one or more managing circuits dynamically adjust said first trigger.

36. A non-volatile storage apparatus according to claim 30, wherein:

said one or more managing circuits adjust said first trigger based on temperature.

37. A non-volatile storage apparatus according to claim 30, wherein:

said one or more managing circuits adjust said first trigger based on number of program cycles.

38. A non-volatile storage apparatus, comprising:

a plurality of non-volatile storage elements including a first group of non-volatile storage elements and a second group of non-volatile storage elements; and

one or more managing circuits in communication with said non-volatile storage elements, said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements, said one or more managing circuits verify said first group of non-volatile storage elements together with verifying said second group of non-volatile storage elements, said one or more managing circuits program said first group of non-volatile storage elements separately from programming said second group of non-volatile storage elements prior to detecting a condition, said one or more managing circuits program said first group of non-volatile storage elements together with said second group of non-volatile storage elements together subsequent to and in response to detecting said condition.

41. A non-volatile storage apparatus, comprising:

a plurality of non-volatile storage elements;

means for performing programming on a first group of said non-volatile storage elements at a first time and for performing programming on a second group of said non-volatile storage elements at a second time different from said first time, said performing programming on said first group of non-volatile storage elements at said first time and said performing programming on said second group of non-volatile storage elements at said second time are performed after and in response to a first trigger;

means for performing one or more program cycles prior to said first trigger, each of said one or more program cycles includes programming said first group of non-volatile storage elements and said second group of non-volatile storage elements together; and

means for verifying said first group of said non-volatile storage elements and said second group of said non-volatile storage elements together.

42. An apparatus according to claim 41, further comprising:

a first control line, said first group of said non-volatile storage elements are connected to said first control line, said second group of said non-volatile storage elements are connected to said first control line.

43. An apparatus according to claim 41, further comprising:

a word line, said first group of said non-volatile storage elements are connected to the word line, said second group of said non-volatile storage elements are connected to said word line, each non-volatile storage element of said first group of said non-volatile storage elements and said second group of said non-volatile storage elements are connected to different bit lines in an interleaving manner.

44. An apparatus according to claim 41, wherein said means for performing programming comprises:

means for applying a first program pulse to said first group of said non-volatile storage elements and said second group of non-volatile storage elements, inhibiting said second group of said non-volatile storage elements from programming in response to said first program pulse, and allowing said first group of said non-volatile storage elements to program in response to said first program pulse; and

means for applying a second program pulse to said first group of said non-volatile storage elements and said second group of said non-volatile storage elements, inhibiting said first group of said non-volatile storage elements from programming in response to said second program pulse, and allowing said second group of said non-volatile storage elements to program in response to said second program pulse.

45. An apparatus according to claim 44, further comprising:

word lines and bit lines, each non-volatile storage element of said first group of said non-volatile storage elements and said second group of said non-volatile storage elements are connected to different bit lines, said bit lines include even bit lines and odd bit lines, said first group of said non-volatile storage elements are connected to said even bit lines and said second group of said non-volatile storage elements are connected to said odd bit lines, said first group of said non-volatile storage elements is arranged in an interleaving manner with said second group of said non-volatile storage elements.

46. An apparatus according to claim 41, wherein said means for verifying said first group of non-volatile storage elements and said second group of non-volatile storage elements together includes:

means for applying one or more verify signals to a word line connected to said first group of said non-volatile storage elements and said second group of said non-volatile storage elements, and simultaneously sensing said first group of said non-volatile storage elements and said second group of said non-volatile storage elements.

47. An apparatus according to claim 41, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements do not have any non-volatile storage elements in common;

said verifying is performed at a third time that is subsequent to said second time;

said second time is subsequent to said first time; and

no verification of said first group of non-volatile storage elements and said second group of non-volatile storage elements is performed between said first time and said second time.

48. An apparatus according to claim 41, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements are flash memory devices.

49. An apparatus according to claim 41, wherein:

said first group of non-volatile storage elements and said second group of non-volatile storage elements are NAND flash memory devices.