Semiconductor memory device, and method of controlling the same

• US 7,869,296 B2
• Filed: 09/06/2006
• Issued: 01/11/2011
• Est. Priority Date: 11/09/1999
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Fujioka, Shinya, Sato, Kotoku, Nishimura, Koichi, Kawakubo, Tomohiro
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/515,852
• Publication Number:
  US 20070002664A1
• Time in Patent Office: 1,588 Days
• Field of Search: 365/222, 365/226, 365/227, 365/228, 365/229, 365/185.04, 365/185.08, 365/185.33, 365/203, 438/257, 345/507, 327/108
• US Class Current: 365/222
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Claims

1. A method of operating a semiconductor memory including dynamic memory cells, comprising:

entering a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations while a power supply voltage is supplied to the semiconductor memory, in response to a single external control signal supplied from an outside via an external control terminal,

wherein the power supply voltage continues to be supplied to the semiconductor memory during the low power consumption mode, and

wherein the semiconductor memory includes a booster, a precharging voltage generator and a substrate voltage generator.

2. The method of operating a semiconductor memory according to claim 1, wherein the semiconductor memory enters the low power consumption mode in response to a voltage change of the single external control signal from a first voltage to a second voltage.

3. The method of operating a semiconductor memory according to claim 2, wherein the low power consumption mode is maintained while the single external control signal keeps the second voltage.

4. The method of operating a semiconductor memory according to claim 2, wherein the semiconductor memory exits the low power consumption mode in response to a reverse voltage change of the single external control signal from the second voltage to the first voltage.

5. A method of controlling a semiconductor memory including dynamic memory cells, comprising:

outputting a single control signal to an external control terminal of the semiconductor memory so that the semiconductor memory enters a low power consumption mode, in which the dynamic memory cells do not retain data therein by prohibiting refresh operations while a power supply voltage is supplied to the semiconductor memory,

wherein the power supply voltage continues to be supplied to the semiconductor memory during the low power consumption mode, and

wherein the semiconductor memory includes a booster, a precharging voltage generator and a substrate voltage generator.

6. The method of controlling the semiconductor memory according to claim 5, further including:

changing a voltage of the single control signal from a first voltage to a second voltage when outputting the single control signal.

7. The method of controlling the semiconductor memory according to claim 6, further comprising:

keeping the voltage of the single control signal at the second voltage to maintain the low power consumption mode of the semiconductor memory.

8. The method of controlling the semiconductor memory according to claim 6, further comprising:

changing the voltage of the single control signal from the second voltage to the first voltage so that the semiconductor memory exits the low power consumption mode.

9. A memory system comprising:

a first memory including dynamic memory cells, having a low power consumption mode and a data terminal, the low power consumption mode being a mode in which the dynamic memory cells do not retain data therein by prohibiting refresh operations while a power supply voltage is supplied to the first memory, and the mode entered in response to a single external control signal supplied from an outside via an external control terminal; and

a second memory including flash memory cells, having a data terminal which is connected with the data terminal of the first memory,

wherein the power supply voltage continues to be supplied to the first memory during the low power consumption mode, and

wherein the first memory includes a booster, a precharging voltage generator and a substrate voltage generator.

10. The memory system according to claim 9, wherein data stored in the dynamic memory cells in the first memory is transferred to the flash memory cells in the second memory before the first memory enters the low power consumption mode.

11. The memory system according to claim 9, wherein data stored in the flash memory cells in the second memory is transferred to the dynamic memory cells in the first memory after the first memory exits the low power consumption mode.

12. A cellular phone having a service state and a waiting state, comprising:

a first memory including dynamic memory cells, having a low power consumption mode, a data terminal, and an external control terminal, the low power consumption mode being a mode in which the dynamic memory cells do not retain data therein while a power supply voltage is supplied to the first memory by prohibiting refresh operations, and the external control terminal being for receiving a single external control signal; and

a second memory including flash memory cells, having a data terminal which is connected with the data terminal of the first memory,

wherein data stored in the dynamic memory cells in the first memory is transferred to the flash memory cells in the second memory then the first memory enters the low power consumption mode in response to the single external control signal upon shifting from the service state to the waiting state,

wherein the first memory exits the low power consumption mode in response to the single external control signal, and then data stored in the flash memory cells in the second memory is transferred to the dynamic memory cells in the first memory upon shifting from the waiting state to the service state,

wherein the power supply voltage continues to be supplied to the first memory during the low power consumption mode, and

wherein the first memory includes a booster, a precharging voltage generator and a substrate voltage generator.

13. A method of controlling a first memory including dynamic memory cells, having a low power consumption mode, a first data terminal, and an external control terminal, the low power consumption mode being a mode in which the dynamic memory cells do not retain data therein by prohibiting refresh operations while a power supply voltage is supplied to first memory, and the external control terminal being for receiving a single external control signal, and a second memory including flash memory cells and a second data terminal connected with the first data terminal of the first memory, comprising:

transferring data stored in the dynamic memory cells in the first memory to the flash memory cells in the second memory via the first and second data terminals before the first memory enters the low power consumption mode in response to the single external control signal; and

transferring data stored in the flash memory cells in the second memory to the dynamic memory cells in the first memory via the second and first data terminals after the first memory exits the low power consumption mode in response to the single external control signal,

wherein the power supply voltage continues to be supplied to the first memory during the low power consumption mode, and

wherein the first memory includes a booster, a precharging voltage generator and a substrate voltage generator.