Frequency-domain decision feedback equalizing device and method

• US 7,869,497 B2
• Filed: 07/31/2003
• Issued: 01/11/2011
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Tomasin, Stefano, Agarossi, Luigi, Benvenuto, Nevio
• Primary Examiner(s): Liu; Shuwang
• Assistant Examiner(s): Neff; Michael R
• Application Number:
  US10/525,597
• Publication Number:
  US 20050259727A1
• Time in Patent Office: 2,721 Days
• Field of Search: 375/233
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/0342 QAM
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03522 Frequency domain
• CPC Class Codes: H04L 2025/03605 Block algorithms
• CPC Class Codes: H04L 2025/0377 during the reception of training signals
• CPC Class Codes: H04L 2025/03789 Codes therefore
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence

Abstract

A fast Fourier transformation is performed on a first vector of signals, and as a result a second vector of signals is provided. A feed forward equalization is performed by multiplying each of the components of said second vector with equalization parameters, and as a result a third vector of signals is provided. An inverse fast Fourier transformation is performed on said third vector, and as a result a fourth vector of signals is provided. An output signal of said first section is provided on the basis of said fourth vector of signals. In a second section a signal derived from an output signal of said second section is is filtered via linear feedback filtering and the filtered signal is added to said first section output signal, and an added signal is provided, and said second section output signal is generated by extracting samples from said added signal.

Claims

1. A frequency-domain decision feedback equalizer device for single carrier modulation comprising:

a first section configured to generate an output signal and including

a fast Fourier transformation circuit configured to perform a fast Fourier transformation on a first vector of signals inputted into said first section, and outputting a second vector of signals,

a feed forward equalizer circuit configured and coupled to perform feed forward equalization by multiplying each of the components of said second vector of signals with equalization parameters, and outputting a third vector of signals, and

an inverse fast Fourier transformation circuit configured and coupled to perform an inverse fast Fourier transformation on said third vector of signals, and outputting a fourth vector of signals; and

a second section including

a feedback filter circuit configured and coupled to perform linear filtering of a signal derived from an output signal of said second section,

an adder circuit coupled to add the output signal of said feedback filter circuit to the output signal of said first section, and

a detector circuit configured and coupled to receive the output signal of said adder circuit and generate said output signal of said second section by extracting samples from the output signal of said adding means.

2. The device according to claim 1, wherein said feed forward equalizer circuit generates equalization parameters adapted for minimizing the signal-to-noise ratio of the signal processed in the frequency-domain decision feedback equalizer device, preferably in the output signal of said first section.

3. The device according to claim 1, wherein said feed forward equalizer circuit generates equalization parameters by taking into account a fast Fourier transformation estimation of a channel impulse response of the signal processed in the frequency-domain decision feedback equalizer device, preferably in the output signal of said first section.

4. The device according to claim 1, wherein said first section further comprises:

a serial to parallel converter circuit coupled to convert a sequence of signals input into said first section to said first vector of signals, and

a parallel to serial converter circuit coupled to convert said fourth vector of signals to a sequence of output signals of said first section.

5. The device according to claim 4, wherein said serial to parallel converter circuit is adapted to receive scalar signals.

6. The device according to claim 4, wherein said serial to parallel converter circuit generates said first vector of signals including blocks of a predetermined number of consecutive samples of the signals input into said first section.

7. The device according to claim 4, wherein said parallel to serial converter circuit and said feedback filter means are configured to output scalar signals.

8. The device according to claim 6, wherein said parallel to serial converter circuit is configured to output a scalar signal which is constituted by consecutive blocks of a predetermined number of samples, each block being built with the predetermined number of samples of each block of said fourth vector of signals.

9. The device according to claim 1, wherein said detector circuit is configured to receive and output discrete time signals.

10. The device according to claim 1, wherein said detector circuit is configured to generate said output signal of the second section.

11. The device according to claim 1, wherein said second section further comprises a feedback input generator for receiving said output signal of said second section and providing an output signal which is built by consecutive blocks, each block including first a pseudo noise sequence and second a predetermined number (M) of samples from said output signal of said section, to said feedback filter circuit.

12. The device according to claim 1, further including a receiver of a communication system using a single carrier modulation, wherein said receiver includes said first and second sections of the frequency-domain decision feedback equalizer device.

13. The device according to claim 1, further including a communication system including a transmitter using a single carrier modulation, for transmitting data, comprising a modulator circuit configured to organize the data in blocks wherein each block is separated by a sequence of a predetermined signal and a receiver of a communication system using a single carrier modulation, wherein said receiver includes said first and second sections of the frequency-domain decision feedback equalizer device.

26. The device according to claim 11, wherein:

the detector circuit is configured to receive and output discrete time signals selected from a constellation consisting of a set of symbols; and

wherein the pseudo noise sequence is constructed from symbols selected from the constellation.

27. The device according to claim 11, wherein:

the detector circuit is configured to receive and output discrete time signals selected from a first constellation consisting of a set of symbols; and

wherein the pseudo noise sequence is a selected sequence constructed from symbols selected from a second constellation exclusive to the first constellation.

28. The device according to claim 11, wherein:

the detector circuit is configured to output scalar signals including a number of samples consisting of the predetermined number (M) of consecutive samples; and

the feedback input generator is configured to output the pseudo noise sequence appended to the scalar signal.

14. A frequency-domain decision feedback equalizing method for single carrier modulation, preferably for use in a broadband communication system, comprising the steps of:

in a first section providing an output signal of said first section by;

performing a fast Fourier transformation on a first vector of signals inputted, and as a result providing a second vector of signals,

performing a feed forward equalization by multiplying each of the components of said second vector of signals with equalization parameters, and as a result providing a third vector of signals,

performing an inverse fast Fourier transformation on said third vector of signals, and as a result providing a fourth vector of signals, and

providing an output signal of said first section on the basis of said fourth vector of signals; and

in a second section;

performing a linear feedback filtering of a signal derived from an output signal of said second section, and providing a filtered signal,

adding said filtered signal to said output signal of said first section, and providing an added signal, and

generating said output signal of said second section by extracting samples from said added signal.

15. The method according to claim 14, wherein in said feed forward equalization step equalization parameters are generated adapted for minimizing the signal-to-noise ratio of the signal processed, preferably in the output signal of said first section.

16. The method according to claim 14, wherein in said feed forward equalization step equalization parameters are generated by taking into account a fast Fourier transformation estimation of a channel impulse response of the signal processed, preferably in the output signal of said first section.

17. The method according to claim 14, comprising in said first section the further steps of:

serial to parallel converting a sequence of signals inputted into said first section to said first vector of signals, and

parallel to serial converting said fourth vector of signals to a sequence of output signals of said first section.

18. The method according to claim 17, wherein said serial to parallel converting step is provided to process scalar signals.

19. The method according to claim 17, wherein said serial to parallel converting step is provided to generate said first vector of signals including blocks of a predetermined number of consecutive samples of the signals inputted into said first section.

20. The method according to claim 17, wherein said parallel to serial converting step and said linear feedback filtering step are provided to output scalar signals.

21. The method according to claim 19, wherein said parallel to serial converting step is provided to output a scalar signal which is constituted by consecutive blocks of a predetermined number of samples, each block being built with the predetermined number of samples of each block of said fourth vector of signals.

22. The method according to claim 14, wherein said extracting step in said second section is adapted to process discrete time signals.

23. The method according to claim 14, wherein said extracting step in said second section is provided to generate said output signal.

24. The method according to claim 14, comprising in said second section a feedback input generating step for processing said output signal of said second section and providing an output signal which is built by consecutive blocks, each block including first a pseudo noise sequence and second a predetermined number of samples from said output signal of said section, to said feedback filter means.

25. A frequency-domain decision feedback equalizer device for single carrier modulation, the device comprising:

a first section including

a fast Fourier transformer to perform a fast Fourier transformation on a first vector of single carrier signals inputted into said first section, and to output the transformed signals as a second vector of signals,

a feed forward equalizer to perform a feed forward equalization by generating equalization parameters using a fast Fourier transformation estimation of a channel impulse response of an output single carrier signal of said first section, multiplying each of the components of said second vector of signals with the generated equalization parameters to reduce the signal-noise ratio of the signals, and outputting the multiplied signals as a third vector of signals, and

an inverse fast Fourier transformer to perform an inverse fast Fourier transformation on said third vector of signals, and to output the inversely transformed signals as a fourth vector of signals that is the output signal of the first section; and

a second section including

a feedback filter to linearly filter a signal derived from an output signal of said second section,

an adder to add the output signal of said feedback filter to the output signal of said first section, and

a detector to receive the output signal of said adder and generate said output signal of said second section by extracting samples from the output signal of said adder.