Multiprocessor system and method thereof

• US 7,870,326 B2
• Filed: 06/28/2007
• Issued: 01/11/2011
• Est. Priority Date: 07/28/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Soo-Young, Lee, Ho-Cheol, Shin, Yun-Hee, Sohn, Han-Gu, Lee, Young-Min, Lee, Chang-Ho, Lee, Dong-Hyuk
• Primary Examiner(s): Song; Jasmine
• Application Number:
  US11/819,601
• Publication Number:
  US 20080172516A1
• Time in Patent Office: 1,293 Days
• Field of Search: 711/5, 711/131, 711147-149, 365/230.05
• US Class Current: 711/5
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00

Abstract

A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

Claims

1. A method of assigning bank addresses to select banks, in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, a second memory bank coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising:

assigning bank addresses to select the first and second memory banks, as respectively separate bank addresses through the first and second ports; and

assigning bank addresses to select the third memory bank, as the same bank address through the first and second ports.

2. A method of assigning bank addresses to select banks, in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, a second memory bank coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising:

assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting; and

assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports.

3. The method of claim 2, wherein the starting address is a starting bank address or staring memory cell address.

4. A method of assigning bank addresses to select banks, in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, a second memory bank coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising:

assigning bank addresses to select individually the first and second memory banks, as different bank addresses through the first and second ports; and

assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports.

5. A method of assigning bank addresses to select banks, in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, a second memory bank coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising:

assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting; and

assigning bank addresses to select the third memory bank, as the same bank address through the first and second ports.

6. A method of assigning bank addresses to select banks in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, a second memory bank coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising:

assigning bank addresses to select the first and second memory banks, as respectively separate bank addresses through the first and second ports; and

assigning bank addresses to select the third memory bank, as the same bank address through the first and second ports, so that starting addresses for the third memory bank become equal in the first and second ports in booting.

7. A method of assigning bank addresses to select banks in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, a second memory bank coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising;

assigning bank addresses to select the first and second memory banks, as respectively separate bank addresses through the first and second ports; and

assigning bank addresses to select the third memory bank, as the same bank address through the first and second ports, so that memory cell addresses for the third memory bank become equal in the first and second ports in booting.

8. A method of assigning bank addresses to select banks, in a semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to a first processor through a first port, second and fourth memory banks coupled to a second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, the method comprising:

assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting;

assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports; and

assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port, whereby with an unused bank address.

9. A data communication system comprising:

first and second processors;

a volatile semiconductor memory device having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, a second memory bank coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports; and

a bank address assigning unit, the bank address assigning unit being operationally connected between the first and second processors and the volatile semiconductor memory device, and being for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and being for assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports.

10. A data processing system comprising:

first and second processors;

a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports; and

a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

11. A method of assigning bank addresses, in a multipath accessible semiconductor memory device including at least one shared memory area and private memory areas in a memory cell array, the at least one shared memory area being operationally connected with ports independently installed corresponding to the number of plural processors, and being selectively accessed by the plural processors, and the private memory areas being privately accessed corresponding to the plural processors, the method comprising:

assigning bank addresses so as to cause all starting bank addresses of a private memory area corresponding to each of the ports, to become equal to each other.

12. A method of assigning bank addresses, in a multipath accessible semiconductor memory device including at least one shared memory area and private memory areas in a memory cell array, the at least one shared memory area being operationally connected with ports independently installed corresponding to the number of plural processors, and being selectively accessed by the plural processors, and the private memory areas being privately accessed corresponding to the plural processors, the method comprising:

assigning bank addresses to cause all starting bank addresses of a private memory area corresponding to each of the ports become different from each other.