System and method for optimizing interconnections of components in a multichip memory module

• US 7,870,329 B2
• Filed: 05/03/2006
• Issued: 01/11/2011
• Est. Priority Date: 04/08/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Janzen, Jeffery W.
• Primary Examiner(s): Thai; Tuan V.
• Application Number:
  US11/417,389
• Publication Number:
  US 20060200598A1
• Time in Patent Office: 1,714 Days
• Field of Search: 711/100, 711/103, 711/104, 711/105, 711/115, 711/154
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

Claims

1. A memory module, comprising:

a circuit board;

a memory hub positioned on the circuit board;

a plurality of memory devices positioned around the memory hub and arranged in pairs, each pair of memory devices having the memory devices positioned orthogonally to one another;

a plurality of data busses, each data bus electrically coupled to the memory hub and a respective one of the plurality of memory devices, the data busses coupled to the memory devices of a pair routed perpendicular to one another; and

a plurality of command-address busses, each command-address bus coupling two adjacent memory devices to the memory hub, each command-address bus having a portion routed at an angle relative to the data busses; and

a connector coupled to the memory hub and configured to couple at least one of command, address, and data signals to the memory hub.

2. The memory module of claim 1 wherein the plurality of memory devices comprises two pairs of memory devices.

3. The memory module of claim 1 wherein the plurality of memory devices comprises a plurality of memory devices having a same arrangement of electrical terminals.

4. A method for routing signal busses of a memory module having a memory hub and a plurality of memory devices arranged around the memory hub, the method comprising:

routing a plurality of data busses electrically coupling the memory hub to a respective one of the memory devices, the data busses coupled to two adjacent memory devices routed parallel to one another;

routing a plurality of command-address busses electrically coupling the memory hub to the memory devices of the plurality, each of the command-address busses coupling two adjacent memory devices to the memory hub, the two adjacent memory devices coupled to a command-address bus being different than the two adjacent memory devices coupled to data busses routed parallel to one another.

5. The method of claim 4 wherein routing a plurality of data busses comprises routing a first pair of data busses coupled to two adjacent memory devices perpendicular to a second pair of data busses coupled to another two adjacent memory devices.

6. The method of claim 5 wherein routing a plurality of command-address busses comprises routing each command-address bus to have a portion at an angle relative to the data busses.

7. The method of claim 6 wherein each of the command-address busses includes another portion perpendicular to the angled portion.

8. The method of claim 5 wherein routing a plurality of command-address busses comprises routing each command-address bus to have a portion at an angle relative to the orientation of the memory devices.