×

Power-aware line intervention for a multiprocessor snoop coherency protocol

  • US 7,870,337 B2
  • Filed: 11/28/2007
  • Issued: 01/11/2011
  • Est. Priority Date: 11/28/2007
  • Status: Active Grant
First Claim
Patent Images

1. A method for intervening a shared cache line in a multiprocessor data processing system, comprising:

  • generating a request from a master processor for a first cache line during operation of said multiprocessor data processing system;

    assembling at the master processor a plurality of partial responses from each of a plurality of memory sources which store a copy of the requested first cache line;

    collecting a temperature or power dissipation value for each of the plurality of memory sources;

    selecting a first memory source from the plurality of memory sources to intervene the requested first cache line, where the first memory source is selected at least in part based on having an acceptable temperature or power dissipation value; and

    broadcasting from the master processor a selection message to instruct the first memory source to intervene the requested first cache line to the master processor.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×