Power-aware line intervention for a multiprocessor snoop coherency protocol

• US 7,870,337 B2
• Filed: 11/28/2007
• Issued: 01/11/2011
• Est. Priority Date: 11/28/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bell, Robert H. Jr., Cook, Thomas E., Shapiro, Michael J., Capps, Louis B. Jr., Nayar, Naresh
• Primary Examiner(s): Thomas; Shane M
• Assistant Examiner(s): Dudek, Jr.; Edward J
• Application Number:
  US11/946,249
• Publication Number:
  US 20090138660A1
• Time in Patent Office: 1,140 Days
• Field of Search: 711/118, 711/154, 711/E12.041, 702/60, 702/64
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

Claims

1. A method for intervening a shared cache line in a multiprocessor data processing system, comprising:

generating a request from a master processor for a first cache line during operation of said multiprocessor data processing system;

assembling at the master processor a plurality of partial responses from each of a plurality of memory sources which store a copy of the requested first cache line;

collecting a temperature or power dissipation value for each of the plurality of memory sources;

selecting a first memory source from the plurality of memory sources to intervene the requested first cache line, where the first memory source is selected at least in part based on having an acceptable temperature or power dissipation value; and

broadcasting from the master processor a selection message to instruct the first memory source to intervene the requested first cache line to the master processor.

2. The method of claim 1, where selecting a first memory source comprises selecting a first memory source having a first temperature or power dissipation value that is lower than a second temperature or power dissipation value associated with a second memory source.

3. The method of claim 1, where selecting a first memory source comprises selecting a cool memory source based at least in part on comparing a first temperature or power dissipation value that is associated with the first memory source to one or more other temperature or power dissipation values associated with one or more other memory sources.

4. The method of claim 1, where the plurality of memory sources comprises a plurality of cache memories.

5. The method of claim 1, where each of the plurality of memory sources comprises a sensor for measuring a temperature or power dissipation value associated with said memory source.

6. The method of claim 4, where selecting a first memory source comprises selecting a memory controller having an acceptable temperature or power dissipation value to intervene the requested first cache line if none of the plurality of cache memories has an acceptable temperature or power dissipation value.

7. The method of claim 1, further comprising snooping at each of the plurality of memory sources for the request from the master processor.

8. The method of claim 1, where broadcasting from the master processor a selection message comprises instructing the plurality of memory sources to invalidate each respective copy of the requested first cache line when the request from the master processor comprises a request for exclusive access to the first cache line.

9. A computer-usable medium embodying computer program code, the computer program code comprising computer executable instructions configured for intervening a shared cache line in a multiprocessor data processing system by:

generating a request from a master processor for a first cache line during operation of said multiprocessor data processing system;

assembling at the master processor a plurality of partial responses from each of a plurality of memory sources which store a copy of the requested first cache line;

collecting a temperature or power dissipation value for each of the plurality of memory sources;

selecting a first memory source from the plurality of memory sources to intervene the requested first cache line, where the first memory source is selected at least in part based on having an acceptable temperature or power dissipation value; and

broadcasting from the master processor a selection message to instruct the first memory source to intervene the requested first cache line to the master processor.

10. The computer-usable medium of claim 9, where selecting a first memory source comprises selecting a first memory source having a first temperature or power dissipation value that is lower than a second temperature or power dissipation value associated with a second memory source.

11. The computer-usable medium of claim 9, where selecting a first memory source comprises selecting a cool memory source based at least in part on comparing a first temperature or power dissipation value that is associated with the first memory source to one or more other temperature or power dissipation values associated with one or more other memory sources.

12. The computer-usable medium of claim 9, where the plurality of memory sources comprises a plurality of cache memories.

13. The computer-usable medium of claim 9, where each of the plurality of memory sources comprises a sensor for measuring a temperature or power dissipation value associated with said memory source.

14. The computer-usable medium of claim 12, where selecting a first memory source comprises selecting a memory controller having an acceptable temperature or power dissipation value to intervene the requested first cache line if none of the plurality of cache memories has an acceptable temperature or power dissipation value.

15. The computer-usable medium of claim 9, further comprising computer executable instructions configured for intervening a shared cache line in a multiprocessor data processing system by snooping at each of the plurality of memory sources for the request from the master processor.

16. The computer-usable medium of claim 9, where broadcasting from the master processor a selection message comprises instructing the plurality of memory sources to invalidate each respective copy of the requested first cache line when the request from the master processor comprises a request for exclusive access to the first cache line.

17. A multiprocessor data processing system comprising:

a plurality of processors, each comprising one or more cache memories;

a data bus coupled to the plurality of processors;

a computer-usable medium embodying computer program code, the computer-usable medium being coupled to the data bus, the computer program code comprising instructions for intervening a shared cache line in a multiprocessor data processing system by;

generating a request from a master processor for a first cache line during operation of said multiprocessor data processing system;

assembling at the master processor a plurality of partial responses from each of a plurality of cache memories which store a copy of the requested first cache line;

collecting a temperature or power dissipation value for each of the plurality of cache memories;

selecting a first cache memory from the plurality of cache memories to intervene the requested first cache line, where the first cache memory is selected at least in part based on having an acceptable temperature or power dissipation value; and

broadcasting from the master processor a selection message to instruct the first cache memory to intervene the requested first cache line to the master processor.

18. The data processing system of claim 17, where selecting a first cache memory comprises selecting a first cache memory having a first temperature or power dissipation value that is lower than a second temperature or power dissipation value associated with a second cache memory.

19. The data processing system of claim 17, further comprising a sensor positioned at each cache memory for measuring a temperature or power dissipation value associated with said cache memory.

20. The data processing system of claim 17, where the sensor comprises a diode.