Data processing system

• US 7,870,347 B2
• Filed: 08/19/2004
• Issued: 01/11/2011
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: Network System Technologies LLC
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Van Der Wolf, Pieter, Van Eijndhoven, Josephus Theodorus Johannes, Boonstra, Johannes
• Primary Examiner(s): Elmore, Stephen C
• Assistant Examiner(s): Giardino, Jr., Mark A
• Application Number:
  US10/570,236
• Publication Number:
  US 20070028038A1
• Time in Patent Office: 2,336 Days
• Field of Search: 710/110, 711/151, 711/168
• US Class Current: 711/151
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).

Claims

1. A data processing system comprising:

memory device and a plurality of data processors accessing said memory device,

at least one local memory unit associated with corresponding ones of said plurality of data processors, said local memory unit adapted to be selectively accessed by a memory access request of corresponding ones of said data processors, wherein said memory device and said local memory unit have a single address space and an address range within said single address space distinguishes between a memory access to said memory device and said local memory unit,

a communication interface coupled between said memory device and said plurality of data processors and said at least one local memory unit, said communication interface including;

a network of nodes and a memory interface, each node comprising at least one slave port for receiving a memory access request from a data processor or from a previous node and at least one master port for issuing a memory access request to a next node or to said memory device in accordance with the memory access request received at said slave port, wherein a corresponding one of the at least one master port is associated with a corresponding address range, wherein one or more slave ports are connected to a master port of a previous node, or to one of said data processors, and one or more said master ports are connected to the memory interface, wherein the memory interface arbitrates access to the memory device and said at least one local memory unit concurrently through corresponding master ports associated with corresponding address range based on an address associated with the memory access request, wherein the communication interface is positioned on a single chip, and wherein the memory device is not positioned on the single chip; and

a cache controller, contained within at least one of said nodes, for controlling at least a section of the local memory unit as a cache memory, wherein at least a part of the local memory unit is used to locally store a copy of data residing in other local memories reachable via one of the master ports of the node.

2. The data processing system according to claim 1, wherein at each node the number of said slave ports is higher than the number of said master ports.

3. The data processing system according to claim 1, wherein said network of nodes is hierarchically structured.

4. The data processing system according to claim 3, wherein said network of nodes is arranged in a directed acyclic graph structure.

5. The data processing system according to claim 4, wherein said network of nodes is arranged in a tree structure.

6. The data processing system according to claim 1, wherein said network of nodes include n groups of nodes with n≧

2, wherein each of the slave ports of the nodes of a first group is connected to one of said plurality of data processors, the master ports of the nodes of the n^th group are coupled to said memory device, and each of the slave ports of the nodes of the n^th group is connected to a master port of the nodes of the (n−

1)^th group.

7. The data processing system according to claim 1, wherein said nodes are hubs.

8. The data processing system according to claim 1, wherein at least one node further comprises at least one memory port to which a local memory unit is connected.

9. The data processing system according to claim 1, wherein said communication interface further includes at least one synchronization means for streaming communication between data processors.

10. The data processing system according to claim 9, wherein at least one node includes said synchronization means for streaming communication between the data processors directly or indirectly coupled to said nodes.

11. The data processing system according to claim 9, wherein the local memory unit is configured to provide storage based on a first-in/first-out function and said synchronization means comprises a first-in/first-out administration means for controlling said local memory unit.

12. The data processing system according to claim 1, wherein at least a portion of said plurality of data processors is positioned on said single chip.