Apparatus, system, and method for adapter card failover

• US 7,870,417 B2
• Filed: 04/20/2007
• Issued: 01/11/2011
• Est. Priority Date: 04/20/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Spanel, Carol, Blinick, Stephen L., Song, Cheng-Chung, Walls, Andrew Dale
• Primary Examiner(s): Baderman; Scott T.
• Assistant Examiner(s): TRUONG, LOAN
• Application Number:
  US11/738,142
• Publication Number:
  US 20080263255A1
• Time in Patent Office: 1,362 Days
• Field of Search: 714/4, 714/8, 714/11
• US Class Current: 714/4.11
• CPC Class Codes: G06F 11/2033 switching over of hardware resources
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2046 where the redundant components share persistent storage G06F11/2043 takes precedence

Abstract

An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Claims

1. An apparatus for adapter card failover, the apparatus comprising:

a switch module comprising semiconductor logic and configured to logically connect a first processor complex to an adapter card through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port, receives error messages from the adapter card, and writes to setup registers of the adapter card, the setup registers storing written first data values that configure the switch module and the adapter card to communicate with the first processor complex as the owner processor complex, and the switch module further logically connects a second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port and writes to the setup registers of the adapter card;

a detection module embodied in the second processor complex comprising semiconductor logic and software instructions executing on a processor and configured to detect a failure of the first processor complex; and

a setup module comprising software instructions executing on a processor and configured to modify the switch module by writing second data values to the setup registers of the adapter card from the second processor complex through the second port to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

2. The apparatus of claim 1, wherein the switch module is configured to identify the adapter card as an endpoint in response to a discovery command from the non-owner processor complex.

3. The apparatus of claim 1, wherein the switch module is configured to provide visibility to a device connected to the adapter card in response to a discovery command from the owner processor complex.

4. The apparatus of claim 1, wherein the owner processor complex communicates with a controller of the adapter card through the switch.

5. The apparatus of claim 1, wherein writing the second data values to the setup registers of the adapter card modifies the switch module to logically connect the second processor to the adapter card as the owner processor complex by switching the adapter card from using a control store of a first memory module to a control store of a second memory module.

6. The apparatus of claim 1, wherein the adapter card communicates with the first and second processor complexes using a Peripheral Component Interconnect Express (PCIe) interface.

7. The apparatus of claim 1, wherein the adapter card communicates with the first and second processor complexes using an interface selected from a Peripheral Component Interconnect Extended (PCI-X) interface and a Peripheral Component Interconnect (PCI) interface.

24. The apparatus of claim 5, wherein the owner processor complex initializes the adapter card, the adapter card is a RAID controller adapter card, the non-owner processor complex does not initialize the adapter card and does not receive error messages and status messages from the adapter card, the switch module identifies the adapter card as an endpoint in response to a discovery command from the non-owner processor complex and provides visibility to a device connected to the adapter card in response to a discovery command from the owner processor complex, and the detection module detects the failure of first processor complex if the first processor complex does not communicate with the adapter card during a specified time interval and the first processor complex does not respond to a subsequent query from the detection module.

8. A system for adapter card failover, the system comprising:

a first processor complex in communication with an adapter card;

a second processor complex in communication with the adapter card and comprising a detection module configured to detect a failure of the first processor complex;

the adapter card comprising

a controller configured to manage the adapter card;

a first memory module configured to store a control store comprising software instructions for the controller;

a switch module comprising semiconductor logic and configured to logically connect the first processor complex to the adapter card through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port, receives error messages from the adapter card, and writes to setup registers of the adapter card, the setup registers storing written first data values that configure the switch module and the adapter card to communicate with the first processor complex as the owner processor complex, and the switch module further logically connects the second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port and writes to the setup registers of the adapter card;

the second processor complex further comprising a setup module configured to modify the switch module by writing second data values to the setup registers of the adapter card from the second processor complex through the second port to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

9. The system of claim 8, wherein the switch module is configured to identify the adapter card as an endpoint in response to a discovery command from the non-owner processor complex.

10. The system of claim 8, wherein the switch module is configured to provide visibility to a device connected to the adapter card in response to a discovery command from the owner processor complex.

11. The system of claim 8, wherein the owner processor complex communicates with the controller of the adapter card through the switch.

12. The system of claim 8, wherein writing the second data values to the setup registers oldie adapter card modifies the switch module to logically connect the second processor to the adapter card as the owner processor complex by switching the adapter card from using the control store of the first memory module to a control store of a second memory module.

13. The system of claim 8, wherein the adapter card communicates with the first and second processor complexes using a PCIe interface.

14. The system of claim 8, wherein the adapter card communicates with the first and second processor complexes using an interface selected from a PCI-X interface and a PCI interface.

15. The system of claim 8, wherein the adapter card is configured as an Ethernet controller.

16. The system of claim 8, wherein the adapter card is configured as a Redundant Array of Independent Disks (RAID) controller.

17. The system of claim 8, wherein the adapter card is configured as a storage area network controller.

25. The system of claim 12, wherein the owner processor complex initializes the adapter card, the adapter card is a RAID controller adapter card, the non-owner processor complex does not initialize the adapter card and does not receive error messages and status messages from the adapter card, the switch module identifies the adapter card as an endpoint in response to a discovery command from the non-owner processor complex and provides visibility to a device connected to the adapter card in response to a discovery command from the owner processor complex, and the detection module detects the failure of first processor complex if the first processor complex does not communicate with the adapter card during a specified time interval and the first processor complex does not respond to a subsequent query from the detection module.

18. A method performed by a processor useable medium having a processor readable program executed on a processor, the method comprising:

connecting a switch module of an adapter card to a first processor complex through a first port as an owner processor complex, wherein the owner processor complex manages the adapter card except for a second port, receives error messages from the adapter card and writes to setup registers of the adapter card, the setup registers storing written first data values that configure the switch module and the adapter card to communicate with the first processor complex as the owner processor complex;

connecting a second processor complex to the adapter card through the second port as a non-owner processor complex, wherein the non-owner processor complex manages the second port and writes to the setup registers of the adapter card;

detecting a failure of the first processor complex at the second processor complex; and

modifying the switch module by writing second data values to the setup registers of the adapter card from the second processor complex through the second port to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

19. The method of claim 18, wherein the switch module is configured to identify the adapter card as an endpoint in response to a discovery command from the non-owner processor complex.

20. The method of claim 18, wherein the owner processor complex communicates with a controller of the adapter card through the switch.

21. The method of claim 18, wherein writing the second data values to the setup registers of the adapter cards connect the second processor to the adapter card as the owner processor complex by switching the adapter card from using a control store of a first memory module to a control store of a second memory module.

22. The method of claim 18, wherein the adapter card communicates with the first and second processor complexes using a PCIe interface.

23. The method of claim 18, wherein the adapter card communicates with the first and second processor complexes using an interface selected from a PCI-X interface and a PCI interface.

26. The method of claim 21, wherein the owner processor complex initializes the adapter card, the adapter card is a RAID controller adapter card, the non-owner processor complex does not initialize the adapter card and does not receive error messages and status messages from the adapter card, the switch module identifies the adapter card as an endpoint in response to a discovery command from the non-owner processor complex and provides visibility to a device connected to the adapter card in response to a discovery command from the owner processor complex, and the failure of first processor complex is detected if the first processor complex does not communicate with the adapter card during a specified time interval and the first processor complex does not respond to a subsequent query from the second processor complex.